load_intent
Makes source-intent data available for get_intent after a SystemVerilog load that omitted intent, re-elaborating from captured files or flist.
Instructions
Make the warm source-intent layer available for get_intent. Use after a
SystemVerilog load that did not retain intent; do not call for VHDL or gate-level
Verilog, and prefer load_systemverilog(intent=True) on the initial load.
This is a no-op when the link is already live; otherwise it replaces the
active universe by re-elaborating from explicit or captured flist/files.
Returns intent_loaded; missing inputs produce a structured error.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| top | No | Top module name; omit to reuse the captured or inferred top. | |
| files | No | SystemVerilog source paths; omit to reuse captured load inputs. | |
| flist | No | SystemVerilog file-list path; omit to reuse captured load inputs. |