get_source
Read the bounded SystemVerilog source excerpt for an elaborated object after loading a design to retrieve exact RTL text, file range, and truncation status.
Instructions
Read the bounded SystemVerilog source excerpt that produced an object
(for example, an FF instance maps to its always_ff block). Use after
load_systemverilog when exact source text is needed; use get_intent for
typedef/enum/parameter semantics and do not use for gate-level Verilog.
Returns object, file, start/end range, text, and truncation status without
modifying files; missing paths and source ranges return structured errors.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| path | Yes | Exact hierarchical path to an object from a SystemVerilog load. | |
| context_lines | No | Extra lines before and after the source range; clamped to 0..20. |