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get_source

Read-onlyIdempotent

Read the bounded SystemVerilog source excerpt for an elaborated object after loading a design to retrieve exact RTL text, file range, and truncation status.

Instructions

Read the bounded SystemVerilog source excerpt that produced an object (for example, an FF instance maps to its always_ff block). Use after load_systemverilog when exact source text is needed; use get_intent for typedef/enum/parameter semantics and do not use for gate-level Verilog. Returns object, file, start/end range, text, and truncation status without modifying files; missing paths and source ranges return structured errors.

Input Schema

TableJSON Schema
NameRequiredDescriptionDefault
pathYesExact hierarchical path to an object from a SystemVerilog load.
context_linesNoExtra lines before and after the source range; clamped to 0..20.

Schema Changelog

Changes observed during successful MCP inspections.

  1. Changed2 schema fields changedv0.1.9
    • addedInput schema / properties / context_lines / description
      Added value: +"Extra lines before and after the source range; clamped to 0..20."
    • addedInput schema / properties / path / description
      Added value: +"Exact hierarchical path to an object from a SystemVerilog load."
  2. First observedv0.1.8

TDQS

A4.4/5.0
Behavior4/5

Does the description disclose side effects, auth requirements, rate limits, or destructive behavior?

Annotations already declare readOnly, idempotent, non-destructive, and closed-world. The description still adds real value beyond them: it discloses the return payload (object, file, start/end range, text, truncation status) and error semantics for missing paths/ranges, which the annotations do not cover. It stops short of a 5 only because 'bounded' is left implicit rather than quantified.

Agents need to know what a tool does to the world before calling it. Descriptions should go beyond structured annotations to explain consequences.

Conciseness4/5

Is the description appropriately sized, front-loaded, and free of redundancy?

Front-loads the core action, then routes usage and disclosure in four tight sentences with no filler. Slightly dense but every clause carries distinct information.

Shorter descriptions cost fewer tokens and are easier for agents to parse. Every sentence should earn its place.

Completeness5/5

Given the tool's complexity, does the description cover enough for an agent to succeed on first attempt?

For a two-parameter read tool with no output schema, the description covers purpose, routing, return fields, truncation behavior, and error handling. Nothing an agent needs to invoke it correctly is missing.

Complex tools with many parameters or behaviors need more documentation. Simple tools need less. This dimension scales expectations accordingly.

Parameters3/5

Does the description clarify parameter syntax, constraints, interactions, or defaults beyond what the schema provides?

Schema description coverage is 100%, and both parameters (path, context_lines) are fully documented in the schema, including the 0..20 clamp. The description's phrase 'bounded excerpt' gestures at the range/context behavior but adds no syntax or format detail beyond the schema, so the baseline 3 is appropriate.

Input schemas describe structure but not intent. Descriptions should explain non-obvious parameter relationships and valid value ranges.

Purpose5/5

Does the description clearly state what the tool does and how it differs from similar tools?

States a specific verb ('Read') and resource ('bounded SystemVerilog source excerpt') and clarifies the mapping (an FF instance maps to its always_ff block). It also explicitly distinguishes itself from get_intent and gate-level Verilog, so an agent can disambiguate without opening sibling schemas.

Agents choose between tools based on descriptions. A clear purpose with a specific verb and resource helps agents select the right tool.

Usage Guidelines5/5

Does the description explain when to use this tool, when not to, or what alternatives exist?

Explicit lifecycle guidance ('Use after load_systemverilog when exact source text is needed'), a named alternative for a specific case ('use get_intent for typedef/enum/parameter semantics'), and an exclusion ('do not use for gate-level Verilog'). This is the full when/when-not/alternative triad.

Agents often have multiple tools that could apply. Explicit usage guidance like "use X instead of Y when Z" prevents misuse.