get_source
Retrieve the SystemVerilog source lines that generated a design object, such as a flip-flop instance mapped to its always_ff block. Returns the file, line range, and source text.
Instructions
SystemVerilog source lines that produced an object (FF instance -> its always_ff block). Returns file, range, text.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| path | Yes | ||
| context_lines | No |