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Server Configuration

Describes the environment variables required to run the server.

NameRequiredDescriptionDefault
hostNoHost for streamable-http transport.127.0.0.1
portNoPort for streamable-http transport.8000
transportNoTransport type (stdio or streamable-http).stdio

Capabilities

Features and capabilities supported by this server

CapabilityDetails
tools
{
  "listChanged": false
}
prompts
{
  "listChanged": false
}
resources
{
  "subscribe": false,
  "listChanged": false
}
experimental
{}

Tools

Functions exposed to the LLM to take actions

NameDescription
statusB

Current session: loaded design summary, and whether the intent layer is live (intent_loaded) / re-loadable (intent_loadable).

load_systemverilogB

Elaborate SystemVerilog (files and/or an flist; optional top module). Anonymous lowered objects are addressable by #. intent=True retains naja's in-engine SNL↔slang link for get_intent.

load_verilogA

Load gate-level/structural Verilog netlists. Pair with load_liberty (or load_primitives) so cells resolve to real models; allow_unknown_designs=True blackboxes any module still undefined instead of failing. Gate netlists carry no source info, so get_source/get_intent cannot answer for them.

load_libertyC

Load Liberty cell libraries (defines primitives for gate netlists).

load_primitivesA

Load primitives: built-in by name ('xilinx'|'yosys') or a Python file defining load(db).

save_snapshotA

Persist the design + source index for fast reload (naja-if + sidecar). Tied to the producing najaeda version — load_snapshot rejects a foreign one.

load_snapshotA

Reload a save_snapshot directory in seconds (no re-elaboration). intent=True also re-elaborates the warm intent layer from the flist saved in the snapshot (for get_intent).

reset_universeA

Clear all loaded designs and session state.

resolveA

Resolve a hierarchical path (e.g. 'top.u_uart.tx_o', bit selects and glob in last segment OK) to instance/term/net descriptors with source refs. On failure returns did-you-mean suggestions. kind: instance|term|net.

findC

Glob search names design-wide (pattern with '.' matches full paths). kind: instance|net|port|module|any. Paginated via cursor.

get_hierarchyA

Hierarchy tree under an instance (default top). Lists only non-assign children (real submodules + leaf primitives); assign glue is reported as assign_count, not enumerated. Each child carries a leaf flag (submodule vs leaf primitive). depth<=5; the non-assign set is paginated at the root via limit/cursor (next_cursor/has_more), deeper levels via children_truncated.

get_driversB

What drives this term/net, through the equipotential: leaf drivers (FF/gate instances with pin, model, source ref) and top-level ports. Capped at limit (default 50, max 200) with a truncated flag; no cursor — raise limit to see more.

get_loadsD

What this term/net feeds, through the equipotential: leaf readers (instances with pin, model, source ref) and top-level ports. Mirror of get_drivers; same limit/truncated capping.

trace_coneA

Trace the combinational fanin/fanout cone of a term/net via naja's LogicCone. direction: fanin|fanout. The cone crosses hierarchy and combinatorial arcs and always stops at flops, top ports, and opaque black-box cells. Returns node_count, counts_by_kind, counts_by_model, and a frontier of {flops, ports, blackboxes} with exact counts and lists capped at max_frontier (<=200) with a truncation marker. cross_hierarchy groups the flop frontier by top-level submodule and, under outside_root_subtree, names the frontier registers that live OUTSIDE the cone root's own subtree (the cross-hierarchy answer) — read it directly.

get_sourceC

SystemVerilog source lines that produced an object (FF instance -> its always_ff block). Returns file, range, text.

get_module_cardA

Deterministic module summary: ports, instance counts by model, sequential count, source ref, plus clock/reset candidates — a name-based regex guess, not a structural result; verify before relying on it.

get_statsC

Aggregated instance statistics per model under an instance (default top). Paginated.

get_intentA

Source-level INTENT a netlist erases in lowering (warm-only). Use when the answer is in the SystemVerilog type/declaration, not the flattened gates: enum/typedef state names + encodings (incl. PACKAGE typedefs whose members live in another file), and symbolic PARAMETER expressions (the formula behind a baked-in width). ref: a hierarchical path ('cva6.csr_regfile_i.priv_lvl_q'), a package member ('riscv::PLEN'), or an instance path for its parameters. want: auto | type | fsm_states | parameters. If the intent layer is not loaded, returns a note and you should fall back to get_source.

load_intentB

Make the warm intent layer available for get_intent (naja's in-engine SNL↔slang link). No-op if a load already retained it; otherwise re-elaborates WITH the link from the captured flist/files (pass them after a cold snapshot).

query_pythonA

Escape hatch: run Python against the live design ('naja' raw bindings, 'snl' raw helpers, 'session', 'top' in scope). Prefer the typed tools above; use this only for queries they cannot express. Unsandboxed eval/exec in the server process — read-only by convention, not enforced; operators can turn it off with NAJA_SCOPE_DISABLE_PYTHON. Output capped.

Prompts

Interactive templates invoked by user choice

NameDescription

No prompts

Resources

Contextual data attached and managed by the client

NameDescription

No resources

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