Serve an interactive browser schematic of the current design. Returns a local URL to open on the MCP server's machine; requires the schematic extra. Uses the loaded design and supports anonymous #id instances.

Replace schematic annotations on instances or pins/ports. Returns the local viewer URL and count. Annotations clear when the design changes.

Return the last browser-selected instance as a naja-scope path, or null. Use the returned path with module-card, source, or hierarchy tools.

Inspect the current in-memory session without changing it. Use this before design queries to confirm a design is loaded and whether get_intent is live (intent_loaded) or can be reloaded (intent_loadable). Returns loaded and, when available, the top summary and loaded source files.

Elaborate local SystemVerilog sources into the active design session. Use this for SystemVerilog RTL; use load_vhdl for VHDL (beta), or load_verilog with load_liberty/load_primitives for a structural gate netlist. Requires at least files or flist and changes the in-memory design session. Anonymous lowered objects are addressable by #. defines are preprocessor -D entries ("NAME" or "NAME=VALUE"). allow_unknown_designs=True blackboxes any module still undefined instead of failing (e.g. undelivered hard macros in a partly-open-source design). intent=True retains naja's in-engine SNL↔slang link for get_intent.

Load local gate-level or structural Verilog into the active session. First call load_liberty for Liberty cells or load_primitives for built-ins; use load_systemverilog instead for RTL elaboration. Unknown modules fail unless allow_unknown_designs is true. Gate netlists carry no source info, so get_source/get_intent cannot answer for them.

Load VHDL into the active session (beta, restricted two-state RTL subset). Load dependency/package files first, one call per file, then the top file. Package-only files or entities awaiting generics may return top=null. Use hierarchy, cards and connectivity queries on the elaborated design. SystemVerilog intent recovery is unavailable; source ranges are not guaranteed. Unsupported constructs may fail during beta development. Returns the top summary when elaborated, language and beta status.

Register standard-cell models from local Liberty .lib files in the active session. Use this before load_verilog when a gate netlist instantiates those cells; use load_primitives instead for the built-in Xilinx or Yosys model sets. This changes session state and returns {"ok": true}.

Register primitive models in the active session from either a built-in name (xilinx or yosys) or one local Python file defining load(db). Provide one source; name takes precedence when both are set. A custom file executes unsandboxed Python in the server process, so only use trusted code. Use load_liberty instead for standard-cell .lib files. Returns {"ok": true}.

Write the active design and source metadata to a local directory for fast reload. Use after loading a design; load_snapshot reads the result. Existing snapshot files in the directory may be overwritten. Snapshots are tied to their producing najaeda version, and returns include the saved path.

Load a compatible save_snapshot directory into the active session in seconds instead of re-elaborating. Use load_systemverilog/load_verilog/load_vhdl when no compatible snapshot exists. The directory must match this najaeda version. intent=True also re-elaborates the warm intent layer from the flist saved in the snapshot (for get_intent).

Discard the active design and all in-memory session state. Use before starting an unrelated design; do not use merely to inspect status. This is destructive to the current session but does not delete source or snapshots. Repeating it is safe and returns {"ok": true}.

Resolve a known hierarchical object path to instance, term, or net descriptors with source references. The final segment accepts a glob and bit selects (for example top.u_uart.tx_o[0]). Use find when the path is unknown; use get_hierarchy to browse children. This read-only query requires a loaded design and returns did-you-mean suggestions on failure.

Search case-sensitive object names across the loaded design with a glob. Use this when an exact path is unknown; use resolve once a path is known or get_hierarchy to browse structure. A dot in pattern switches matching to full hierarchical paths. Returns typed descriptors in matches plus count, has_more, and an opaque next_cursor for pagination.

Browse the instance tree below path (or the top instance). Use this for structural children; use find for design-wide name search or get_stats for aggregate model counts. Lists only non-assign children (real submodules + leaf primitives); assign glue is reported as assign_count, not enumerated. Each child carries a leaf flag (submodule vs leaf primitive). depth<=5; the non-assign set is paginated at the root via limit/cursor (next_cursor/has_more), deeper levels via children_truncated.

List the immediate upstream endpoints that drive a term or net across hierarchy. Use this for direct sources; use get_loads for downstream readers or trace_cone for the transitive combinational fanin. Returns leaf drivers (FF/gate instances with pin, model, source ref) and top-level ports. Lowered assign glue is traversed rather than reported as an endpoint. Literal assign drivers include constant (0, 1, X, or Z); bus entries include the driven bit. Capped at limit (default 50, max 200) with a truncated flag; no cursor — raise limit to see more.

List the immediate downstream endpoints that consume a term or net across hierarchy. Use this for direct readers; use get_drivers for upstream sources or trace_cone for the transitive combinational fanout. Returns leaf readers (instances with pin, model, source ref) and top-level ports. Lowered assign glue is traversed rather than reported as an endpoint. Capped at limit (default 50, max 200) with a truncated flag; no cursor — raise limit to see more.

Trace the combinational fanin/fanout cone of a term/net via naja's LogicCone. Use this for transitive logic reachability; use get_drivers or get_loads for only immediate endpoints. direction: fanin|fanout. The cone crosses hierarchy and combinatorial arcs and always stops at flops, top ports, and opaque black-box cells. Returns node_count, counts_by_kind, counts_by_model, and a frontier of {flops, ports, blackboxes} with exact counts and lists capped at max_frontier (<=200) with a truncation marker. cross_hierarchy groups the flop frontier by top-level submodule and, under outside_root_subtree, names the frontier registers that live OUTSIDE the cone root's own subtree (the cross-hierarchy answer) — read it directly.

Read the bounded SystemVerilog source excerpt that produced an object (for example, an FF instance maps to its always_ff block). Use after load_systemverilog when exact source text is needed; use get_intent for typedef/enum/parameter semantics and do not use for gate-level Verilog. Returns object, file, start/end range, text, and truncation status without modifying files; missing paths and source ranges return structured errors.

Deterministic module summary: ports, instance counts by model, sequential count, source ref, plus clock/reset candidates — a name-based regex guess, not a structural result; verify before relying on it. Use this for one model's interface; use get_stats for counts below an instance.

Summarize instance population by model below path or the top design. Use this for aggregate leaf/sequential/model counts; use get_hierarchy for actual child instances or get_module_card for one model's ports. This read-only query requires a loaded design. Returns root_model, flat totals, a paginated models list, total_models, has_more, and next_cursor.

Retrieve source-level intent that netlist lowering erases (warm-only). Use when the answer is in the SystemVerilog type/declaration, not the flattened gates: enum/typedef state names + encodings (incl. PACKAGE typedefs whose members live in another file), and symbolic PARAMETER expressions (the formula behind a baked-in width). ref: a hierarchical path ('cva6.csr_regfile_i.priv_lvl_q'), a package member ('riscv::PLEN'), or an instance path for its parameters. want: auto | type | fsm_states | parameters. If the intent layer is not loaded, returns a note and you should fall back to get_source.

Make the warm source-intent layer available for get_intent. Use after a SystemVerilog load that did not retain intent; do not call for VHDL or gate-level Verilog, and prefer load_systemverilog(intent=True) on the initial load. This is a no-op when the link is already live; otherwise it replaces the active universe by re-elaborating from explicit or captured flist/files. Returns intent_loaded; missing inputs produce a structured error.