get_intent
Retrieve SystemVerilog source intent erased by netlist lowering: enum/typedef state names, encodings, and symbolic parameter expressions from hierarchical paths or package members.
Instructions
Retrieve source-level intent that netlist lowering erases (warm-only). Use when the answer is in the SystemVerilog type/declaration, not the flattened gates: enum/typedef state names + encodings (incl. PACKAGE typedefs whose members live in another file), and symbolic PARAMETER expressions (the formula behind a baked-in width). ref: a hierarchical path ('cva6.csr_regfile_i.priv_lvl_q'), a package member ('riscv::PLEN'), or an instance path for its parameters. want: auto | type | fsm_states | parameters. If the intent layer is not loaded, returns a note and you should fall back to get_source.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| ref | Yes | Hierarchical object/instance path or package member such as pkg::NAME. | |
| want | No | Intent fact to retrieve; auto selects from the reference. | auto |