get_intent
Retrieve source-level type declarations, FSM state names, or parameter expressions from a hierarchical reference. Use when the answer lies in SystemVerilog types instead of the flattened netlist.
Instructions
Source-level INTENT a netlist erases in lowering (warm-only). Use when the answer is in the SystemVerilog type/declaration, not the flattened gates: enum/typedef state names + encodings (incl. PACKAGE typedefs whose members live in another file), and symbolic PARAMETER expressions (the formula behind a baked-in width). ref: a hierarchical path ('cva6.csr_regfile_i.priv_lvl_q'), a package member ('riscv::PLEN'), or an instance path for its parameters. want: auto | type | fsm_states | parameters. If the intent layer is not loaded, returns a note and you should fall back to get_source.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| ref | Yes | ||
| want | No | auto |