rtl_tree
Inspect a SystemVerilog module's instance hierarchy from a file, or set reverse to list parent modules that instantiate it. Use it to trace RTL design structure and connectivity.
Instructions
Module instance hierarchy rooted at the module in file: instance: module (path:line). reverse=true shows the parents that instantiate it instead.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| file | Yes | SystemVerilog file path, absolute or relative to the workspace root | |
| reverse | No |