rename_symbol
Rename a SystemVerilog symbol across the project by specifying its file, line, and new name. Optionally preview the diff before writing changes.
Instructions
Rename symbol (on line of file) to new_name across the project.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| file | Yes | SystemVerilog file path, absolute or relative to the workspace root | |
| line | Yes | 1-based line number | |
| symbol | Yes | Symbol text as written on that line | |
| preview | No | Return the diff without writing (default false) | |
| new_name | Yes | ||
| occurrence | No | Which occurrence on the line, if the symbol appears more than once (default 1) |