document_symbols
Extract a SystemVerilog file outline—modules, ports, signals, parameters, instances, and functions with line numbers—to locate and navigate code structure.
Instructions
Outline of a file: modules, ports, signals, parameters, instances, functions... with line numbers.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| file | Yes | SystemVerilog file path, absolute or relative to the workspace root |