find_references
Lists all project-wide references to a SystemVerilog symbol at a given file and line, helping you trace usage and navigate code during edits.
Instructions
List every reference to symbol (on line of file) across the project.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| file | Yes | SystemVerilog file path, absolute or relative to the workspace root | |
| line | Yes | 1-based line number | |
| symbol | Yes | Symbol text as written on that line | |
| occurrence | No | Which occurrence on the line, if the symbol appears more than once (default 1) | |
| include_declaration | No |