code_actions
Discover available SystemVerilog RTL edits at a specific file and line, optionally targeting a symbol, to identify the appropriate fix or generation step before applying it.
Instructions
List RTL code actions available at line of file: AutoInst (on an instantiation line), AutoArg (module header), AutoFunc, AutoFF (always_ff), AutoWire, add default case, ... Pass symbol to place the cursor on it (e.g. the module name of an instance). Run one with apply_code_action.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| file | Yes | SystemVerilog file path, absolute or relative to the workspace root | |
| line | Yes | 1-based line number | |
| symbol | No | Symbol text as written on that line |