cg_synth
Synthesize Verilog with yosys to verify a design maps to real hardware, catching non-synthesizable constructs and silent failures such as constant-folded datapaths or inferred latches. Run after simulation passes.
Instructions
Synthesize the generated Verilog with yosys — the strongest signal
that a design maps to real hardware (catches non-synthesizable
constructs that simulate/iverilog accept). Returns {ok, verdict, top,
flow, cells, arith_ops, latches, warnings, stat, problems, output}.
verdict is the one-word classification so you can't confabulate
success: REAL (a genuine datapath), FOLDED (0 datapath cells — inputs
weren't on ports, dead hardware), SUSPECT (latches inferred — a
data-dependent loop / missing reset), or ERROR (yosys failed). cells
is the gate count; problems lists any ERROR/Warning lines.
warnings flags the two silent failure modes: a DEGENERATE datapath
(arith_ops == 0 → the design constant-folded; drive it with input
ports) and inferred LATCHES (latches > 0 → a data-dependent loop bound
or incomplete assignment; expected a clocked FSM). A clean synth has
ok: true, a sensible cells, arith_ops > 0, and empty warnings.
NOT a correctness oracle: a REAL verdict means real (synthesizable)
hardware, NOT correct hardware — it can't tell a good sequential FSM
from a buggy one. cg_simulate (the asserting test network) is the
correctness check; run it FIRST, then cg_synth to confirm the hardware
is real, not folded or latched.
top defaults to the first non-testbench task/network (the DUT); pass
it when a file holds several designs. flow selects the synthesis
flow: 'generic' (default, portable check) or a vendor FPGA family —
'ice40', 'ecp5', 'xilinx', 'gowin', 'intel' — to map to that part's
primitives. Override the yosys binary with the $YOSYS env var. Run
after cg_simulate passes. A constant-bound for synthesizes (it's
unrolled); a data-dependent loop becomes an FSM (also fine).
report_dir DEFAULTS to "fpga/build", so each synth automatically records
THIS kernel's verdict + cell counts as a row in /report.html —
synthesizing the kernels builds the whole report as a byproduct, no
separate step (see cg_report). Pass report_dir="" to disable.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| top | No | ||
| flow | No | generic | |
| source | Yes | ||
| timeout | No | ||
| report_dir | No | fpga/build | |
| extra_files | No | ||
| package_dir | No |