cg_generate_verilog
Generate synthesizable Verilog from C-like HDL (C⏚) source. Supports multi-file projects with package resolution and optional disk output for RTL handoff.
Instructions
Generate synthesizable HDL from C⏚. target is 'verilog' (default) or 'vhdl'. Returns {ok, file_count, files:{path:content}}. Use after cg_simulate passes, to hand off RTL.
Pass output_dir (e.g. "fpga/build/verilog", relative to the project
root) to WRITE the files to disk and KEEP them — the result then also
carries {output_dir, written:[paths]}. Without it the files are only
returned inline and the temp dir is cleaned. Prefer output_dir when
the host needs the .v on disk (to inspect or run yosys).
For a MULTI-FILE project, pass package_dir (the folder with your .cg
files) so sibling tasks in the same package resolve during generation.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| source | Yes | ||
| target | No | verilog | |
| output_dir | No | ||
| extra_files | No | ||
| package_dir | No |