cg_simulate
Simulate C-like HDL source code to verify correctness through bytecode or Verilog simulation, returning pass/fail diagnostics and output values.
Instructions
Simulate C⏚ source. Returns {ok, simulator, timed_out, diagnostics,
output}. output holds port values and print() lines; a
properties { test: {...} } block self-checks and fails the run on
mismatch. This is the ground-truth correctness check — iterate until
ok is true.
simulator picks the backend: 'bytecode' (default — the compiler's
fast simulator, no HDL toolchain) or 'iverilog' (generate Verilog +
testbench and run Icarus Verilog, a Verilog-level cross-check; needs a
network <Name>_test). 'verilator' is accepted but reported
unavailable unless installed.
For a MULTI-FILE project, pass package_dir (the folder with your .cg
files, e.g. "fpga/src/main/cg") so every sibling task in the same package
resolves — a cg_example you pulled must be saved to a file in that dir,
not just referenced.
report_dir DEFAULTS to "fpga/build" — this run's PASS/FAIL + output is
recorded into that dir's accumulating report.html (see cg_report). Pass
report_dir="" to disable.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| source | Yes | ||
| timeout | No | ||
| simulator | No | bytecode | |
| report_dir | No | fpga/build | |
| extra_files | No | ||
| package_dir | No |