cg_suggest_for_error
Maps a compiler diagnostic to a synthesizable pattern recipe with hints and source code, enabling resolution of rejected HDL constructs.
Instructions
Map a compiler error/diagnostic to the recipe that demonstrates the
synthesizable pattern for what was rejected. Returns {ok, recipe, hint,
source}. div/shift-by-a-variable → Recip (bit-serial long division);
a data-dependent/runtime loop bound → SeqDiv (sequential FSM divider).
cg_check/cg_simulate/cg_generate_verilog already auto-attach this as a
suggestion when a diagnostic matches; call this directly to look one up.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| message | Yes |