A
licenseA
qualityB
maintenanceEnables AI coding agents and IDEs to lint, compile, syntax-check, and simulate Verilog/SystemVerilog designs through structured, token-efficient MCP tools with isolated containerized toolchains.
4
32 npm
Apache 2.0
cg-agent-kit
by Neosyn-Logic
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TDQS
A4/5.0
Scored across 10 tools
Disambiguation5/5
Each tool targets a distinct stage in the C⏚ hardware design workflow: type-checking, documentation, example retrieval, FSM analysis, HDL generation, graph visualization, reporting, simulation, error-to-recipe mapping, and synthesis. No overlaps are apparent.
Naming Consistency4/5
All tools share the 'cg_' prefix. Most follow a verb_noun pattern (e.g., cg_check, cg_generate_verilog, cg_simulate), but a few use nouns alone (cg_docs, cg_example, cg_fsm, cg_graph). This minor inconsistency slightly reduces clarity but remains acceptable.
Tool Count5/5
With exactly 10 tools, the set is well-scoped for a hardware design assistant. It covers the full front-to-back workflow without being overwhelming or too sparse.
Completeness5/5
The tool surface provides complete lifecycle coverage: code checking, example retrieval, simulation, synthesis, Verilog generation, report finalization, plus supplementary tools for debugging (FSM, graph) and error guidance. No obvious gaps for the stated purpose.
Maintenance
ActivitySlowing
ResponsivenessNo issues