"author:zesun33" matching MCP servers:

Enables AI coding agents and IDEs to perform AST-backed semantic Verilog/SystemVerilog code reviews, catching race conditions, reset polarity mismatches, and bitwidth truncations while computing a 0–100 RTL quality score.

Enables AI coding agents and IDEs to run a complete open-source FPGA flow, including synthesis, place-and-route, bitstream generation, and safe hardware programming for iCE40/ECP5 boards.

Enables AI coding agents and IDEs to execute ASIC physical design flows including floorplanning, placement, clock tree synthesis, routing, and static timing analysis through the OpenROAD engine, returning concise low-token JSON metrics.

Enables AI coding agents and IDEs to lint, compile, syntax-check, and simulate Verilog/SystemVerilog designs through structured, token-efficient MCP tools with isolated containerized toolchains.

Enables running SPICE netlists with ngspice in batch mode and returning .meas results as JSON.

Enables AI coding agents and IDEs to prove SystemVerilog assertions with SymbiYosys (smtbmc+z3) and lint SVA syntax, returning honest verdicts such as PROVEN, FAILED, UNKNOWN, ERROR, or TIMEOUT.

Enables AI agents to run GDSII stream-out, KLayout DRC, Netgen LVS, and Magic extraction via MCP.

Enables AI coding agents and IDEs to synthesize Verilog/SystemVerilog designs with Yosys, inspect cell hierarchies and gate counts, and detect synthesis hazards like inferred latches and combinational loops before physical design flows.

Enables AI coding agents to discover, generate, and run Cocotb co-simulation testbenches against Verilog/SystemVerilog designs, returning structured pass/fail results and tracebacks without manual simulator or Makefile setup.