cg_report
Aggregate synthesis and simulation fragments to render a self-contained HTML FPGA report with verdicts, cell counts, PASS/FAIL status, and optional datapath schematics.
Instructions
Finalize the FPGA report: (re)render <report_dir>/report.html — a self-contained HTML with the synthesis table (REAL/FOLDED/SUSPECT verdict
cell/arith/latch counts), the simulation PASS/FAIL + output, the generated-Verilog file list, and (best-effort) datapath schematic SVGs.
This does NO synthesis — the rows are built incrementally by passing the
SAME report_dir to cg_synth (per kernel) and cg_simulate as you run
them; cg_report just aggregates those fragments + the Verilog under
<report_dir>/verilog and renders. Workflow:
cg_generate_verilog(output_dir="<report_dir>/verilog", package_dir=...)
cg_simulate(..., report_dir="<report_dir>")
cg_synth(..., report_dir="<report_dir>") # once per kernel
cg_report(report_dir="<report_dir>") # finalize + schematics
Returns {ok, report (the .html path), kernels, sim_ok, message}. Set
schematics=False to skip the SVGs (faster).
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| report_dir | No | fpga/build | |
| schematics | No |