synthesize_verilog
Convert Verilog HDL code into optimized gate-level netlists for FPGA implementation using Yosys synthesis, supporting multiple target technologies.
Instructions
Synthesize Verilog code using Yosys for various FPGA targets
Input Schema
TableJSON Schema
| Name | Required | Description | Default |
|---|---|---|---|
| verilog_code | Yes | The Verilog source code to synthesize | |
| top_module | Yes | Name of the top-level module | |
| target | No | Target technology (generic, ice40, xilinx, intel) | generic |
Implementation Reference
- src/index.ts:147-223 (handler)Core handler function in EDAServer class that implements Verilog synthesis using Yosys. Creates temp project dir, writes Verilog, generates target-specific Yosys script (generic/ice40/xilinx), executes yosys, extracts synthesized netlist, and returns JSON with results and project_id.async synthesizeVerilog(verilogCode: string, topModule: string, target = "generic"): Promise<string> { try { const projectId = Math.random().toString(36).substring(2, 15); const projectDir = join(this.tempDir, `project_${projectId}`); await fs.mkdir(projectDir, { recursive: true }); // Store project info this.projects.set(projectId, { dir: projectDir, type: "synthesis" }); // Write Verilog file const verilogFile = join(projectDir, "design.v"); await fs.writeFile(verilogFile, verilogCode); // Create synthesis script let synthScript: string; switch (target.toLowerCase()) { case "ice40": synthScript = ` read_verilog design.v hierarchy -check -top ${topModule} synth_ice40 -top ${topModule} write_verilog synth_output.v stat `; break; case "xilinx": synthScript = ` read_verilog design.v hierarchy -check -top ${topModule} synth_xilinx -top ${topModule} write_verilog synth_output.v stat `; break; default: synthScript = ` read_verilog design.v hierarchy -check -top ${topModule} synth -top ${topModule} techmap opt write_verilog synth_output.v stat `; } const scriptFile = join(projectDir, "synth.ys"); await fs.writeFile(scriptFile, synthScript); // Run Yosys const { stdout, stderr } = await execAsync(`yosys -s ${scriptFile}`, { cwd: projectDir, timeout: 120000, }); let synthVerilog = ""; try { synthVerilog = await fs.readFile(join(projectDir, "synth_output.v"), 'utf8'); } catch { synthVerilog = "Synthesis output not generated"; } return JSON.stringify({ project_id: projectId, success: true, stdout, stderr, synthesized_verilog: synthVerilog, target, }, null, 2); } catch (error: any) { return JSON.stringify({ success: false, error: error.message || String(error), }, null, 2); } }
- src/index.ts:726-748 (registration)Tool registration in ListTools response, including name, description, and input schema (verilog_code required string, top_module required string, target optional string default 'generic').{ name: "synthesize_verilog", description: "Synthesize Verilog code using Yosys for various FPGA targets", inputSchema: { type: "object", properties: { verilog_code: { type: "string", description: "The Verilog source code to synthesize" }, top_module: { type: "string", description: "Name of the top-level module" }, target: { type: "string", description: "Target technology (generic, ice40, xilinx, intel)", default: "generic" }, }, required: ["verilog_code", "top_module"], }, },
- src/index.ts:868-879 (handler)MCP CallToolRequestSchema handler case that validates input parameters using helpers and delegates to edaServer.synthesizeVerilog method.case "synthesize_verilog": { const verilogCode = validateRequiredString(args, "verilog_code", name); const topModule = validateRequiredString(args, "top_module", name); const target = getStringProperty(args, "target", "generic"); return { content: [{ type: "text", text: await edaServer.synthesizeVerilog(verilogCode, topModule, target), }], }; }
- src/index.ts:49-75 (helper)Helper function for executing shell commands with timeout and large buffer support, used by synthesizeVerilog to run Yosys.async function execAsyncWithTimeout(command: string, options: any = {}, timeoutMs = 600000): Promise<{stdout: string, stderr: string}> { return new Promise((resolve, reject) => { const timeout = setTimeout(() => { childProcess.kill('SIGKILL'); reject(new Error(`Command timed out after ${timeoutMs}ms: ${command}`)); }, timeoutMs); // Ensure encoding is set to get string output and increase buffer size const execOptions = { encoding: 'utf8' as const, maxBuffer: 10 * 1024 * 1024, // 10MB default buffer ...options }; const childProcess = exec(command, execOptions, (error, stdout, stderr) => { clearTimeout(timeout); if (error) { reject(error); } else { // Convert to string if needed (though with utf8 encoding it should already be string) const stdoutStr = typeof stdout === 'string' ? stdout : stdout.toString(); const stderrStr = typeof stderr === 'string' ? stderr : stderr.toString(); resolve({ stdout: stdoutStr, stderr: stderrStr }); } }); }); }