synthesize_verilog
Convert Verilog code into optimized FPGA designs for specific target technologies using Yosys. Specify the top module and choose a target (e.g., ice40, xilinx, intel) for precise synthesis results.
Instructions
Synthesize Verilog code using Yosys for various FPGA targets
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| target | No | Target technology (generic, ice40, xilinx, intel) | generic |
| top_module | Yes | Name of the top-level module | |
| verilog_code | Yes | The Verilog source code to synthesize |
Input Schema (JSON Schema)
{
"properties": {
"target": {
"default": "generic",
"description": "Target technology (generic, ice40, xilinx, intel)",
"type": "string"
},
"top_module": {
"description": "Name of the top-level module",
"type": "string"
},
"verilog_code": {
"description": "The Verilog source code to synthesize",
"type": "string"
}
},
"required": [
"verilog_code",
"top_module"
],
"type": "object"
}