Skip to main content
Glama

EDA Tools MCP Server

by NellyW8

synthesize_verilog

Convert Verilog code into optimized FPGA designs using Yosys, supporting generic, ice40, xilinx, and intel targets. Ideal for hardware design workflows.

Instructions

Synthesize Verilog code using Yosys for various FPGA targets

Input Schema

NameRequiredDescriptionDefault
targetNoTarget technology (generic, ice40, xilinx, intel)generic
top_moduleYesName of the top-level module
verilog_codeYesThe Verilog source code to synthesize

Input Schema (JSON Schema)

{ "properties": { "target": { "default": "generic", "description": "Target technology (generic, ice40, xilinx, intel)", "type": "string" }, "top_module": { "description": "Name of the top-level module", "type": "string" }, "verilog_code": { "description": "The Verilog source code to synthesize", "type": "string" } }, "required": [ "verilog_code", "top_module" ], "type": "object" }
Install Server

Other Tools from EDA Tools MCP Server

Related Tools

    MCP directory API

    We provide all the information about MCP servers via our MCP API.

    curl -X GET 'https://glama.ai/api/mcp/v1/servers/NellyW8/mcp-EDA'

    If you have feedback or need assistance with the MCP directory API, please join our Discord server