Server Configuration
Describes the environment variables required to run the server.
| Name | Required | Description | Default |
|---|---|---|---|
| HOME | No | Path to your home directory | |
| PATH | No | System path variable that should include locations of EDA tools | /usr/local/bin:/opt/homebrew/bin:/usr/bin:/bin |
Schema
Prompts
Interactive templates invoked by user choice
| Name | Description |
|---|---|
No prompts | |
Resources
Contextual data attached and managed by the client
| Name | Description |
|---|---|
No resources | |
Tools
Functions exposed to the LLM to take actions
| Name | Description |
|---|---|
| synthesize_verilog | Synthesize Verilog code using Yosys for various FPGA targets |
| simulate_verilog | Simulate Verilog code using Icarus Verilog |
| view_waveform | Open VCD waveform file in GTKWave viewer |
| run_openlane | Run complete ASIC design flow using OpenLane (RTL to GDSII). This process can take up to 10 minutes. |
| view_gds | Open GDSII file in KLayout viewer |
| read_openlane_reports | Read OpenLane report files for LLM analysis. Returns all reports or specific category for detailed analysis of PPA metrics, timing, routing quality, and other design results. |