simulate_verilog
Execute Verilog code simulations with Icarus Verilog by providing design and testbench code to validate hardware designs efficiently.
Instructions
Simulate Verilog code using Icarus Verilog
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| testbench_code | Yes | The testbench code | |
| verilog_code | Yes | The Verilog design code |