simulate_verilog
Execute Verilog code simulations with Icarus Verilog by providing design and testbench code to validate hardware designs efficiently.
Instructions
Simulate Verilog code using Icarus Verilog
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| testbench_code | Yes | The testbench code | |
| verilog_code | Yes | The Verilog design code |
Input Schema (JSON Schema)
{
"properties": {
"testbench_code": {
"description": "The testbench code",
"type": "string"
},
"verilog_code": {
"description": "The Verilog design code",
"type": "string"
}
},
"required": [
"verilog_code",
"testbench_code"
],
"type": "object"
}