simulate_verilog
Run Verilog code simulations with Icarus Verilog by providing design and testbench code. Enable testing and validation of hardware designs within the EDA Tools MCP Server.
Instructions
Simulate Verilog code using Icarus Verilog
Input Schema
Name | Required | Description | Default |
---|---|---|---|
testbench_code | Yes | The testbench code | |
verilog_code | Yes | The Verilog design code |