simulate_verilog
Simulate Verilog designs and testbenches using Icarus Verilog to verify functionality and debug code efficiently. Ideal for digital design validation workflows.
Instructions
Simulate Verilog code using Icarus Verilog
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| testbench_code | Yes | The testbench code | |
| verilog_code | Yes | The Verilog design code |