simulate_verilog
Simulate Verilog designs and testbenches using Icarus Verilog to verify functionality and debug code efficiently. Ideal for digital design validation workflows.
Instructions
Simulate Verilog code using Icarus Verilog
Input Schema
TableJSON Schema
| Name | Required | Description | Default |
|---|---|---|---|
| testbench_code | Yes | The testbench code | |
| verilog_code | Yes | The Verilog design code |
Implementation Reference
- src/index.ts:225-265 (handler)The core implementation of the simulate_verilog tool. This method in the EDAServer class creates a temporary project directory, writes the provided Verilog code and testbench to files, compiles them using iverilog (Icarus Verilog), executes the simulation, captures stdout/stderr from both steps, and returns a structured JSON response including a project_id for viewing waveforms.async simulateVerilog(verilogCode: string, testbenchCode: string): Promise<string> { try { const projectId = Math.random().toString(36).substring(2, 15); const projectDir = join(this.tempDir, `sim_project_${projectId}`); await fs.mkdir(projectDir, { recursive: true }); // Store project info this.projects.set(projectId, { dir: projectDir, type: "simulation" }); // Write design and testbench files await fs.writeFile(join(projectDir, "design.v"), verilogCode); await fs.writeFile(join(projectDir, "testbench.v"), testbenchCode); // Compile and run simulation const compileCmd = `iverilog -o simulation design.v testbench.v`; const { stdout: compileOut, stderr: compileErr } = await execAsync(compileCmd, { cwd: projectDir, timeout: 60000, }); const { stdout: simOut, stderr: simErr } = await execAsync('./simulation', { cwd: projectDir, timeout: 60000, }); return JSON.stringify({ project_id: projectId, success: true, compile_stdout: compileOut, compile_stderr: compileErr, sim_stdout: simOut, sim_stderr: simErr, note: `Use view_waveform with project_id: ${projectId} to open GTKWave` }, null, 2); } catch (error: any) { return JSON.stringify({ success: false, error: error.message || String(error), }, null, 2); } }
- src/index.ts:752-765 (schema)The input schema definition for the simulate_verilog tool, specifying the required verilog_code and testbench_code parameters as strings.inputSchema: { type: "object", properties: { verilog_code: { type: "string", description: "The Verilog design code" }, testbench_code: { type: "string", description: "The testbench code" }, }, required: ["verilog_code", "testbench_code"], },
- src/index.ts:750-766 (registration)Registration of the simulate_verilog tool in the list of tools returned by ListToolsRequestHandler.name: "simulate_verilog", description: "Simulate Verilog code using Icarus Verilog", inputSchema: { type: "object", properties: { verilog_code: { type: "string", description: "The Verilog design code" }, testbench_code: { type: "string", description: "The testbench code" }, }, required: ["verilog_code", "testbench_code"], }, },
- src/index.ts:880-889 (registration)The switch case in the CallToolRequestHandler that routes simulate_verilog calls to the EDAServer.simulateVerilog method after parameter validation.case "simulate_verilog": { const verilogCode = validateRequiredString(args, "verilog_code", name); const testbenchCode = validateRequiredString(args, "testbench_code", name); return { content: [{ type: "text", text: await edaServer.simulateVerilog(verilogCode, testbenchCode), }], };