synthesize_verilog
Convert Verilog code into optimized FPGA designs using Yosys. Specify the top module and target technology for accurate synthesis.
Instructions
Synthesize Verilog code using Yosys for various FPGA targets
Input Schema
TableJSON Schema
| Name | Required | Description | Default |
|---|---|---|---|
| target | No | Target technology (generic, ice40, xilinx, intel) | generic |
| top_module | Yes | Name of the top-level module | |
| verilog_code | Yes | The Verilog source code to synthesize |
Implementation Reference
- src/index.ts:147-223 (handler)The core handler function in the EDAServer class that implements Verilog synthesis using Yosys. It creates a temporary project directory, writes the input Verilog code, generates a target-specific Yosys script (generic, ice40, xilinx), executes Yosys, extracts the synthesized netlist, and returns JSON with results including project_id, stdout, stderr, and synthesized_verilog.async synthesizeVerilog(verilogCode: string, topModule: string, target = "generic"): Promise<string> { try { const projectId = Math.random().toString(36).substring(2, 15); const projectDir = join(this.tempDir, `project_${projectId}`); await fs.mkdir(projectDir, { recursive: true }); // Store project info this.projects.set(projectId, { dir: projectDir, type: "synthesis" }); // Write Verilog file const verilogFile = join(projectDir, "design.v"); await fs.writeFile(verilogFile, verilogCode); // Create synthesis script let synthScript: string; switch (target.toLowerCase()) { case "ice40": synthScript = ` read_verilog design.v hierarchy -check -top ${topModule} synth_ice40 -top ${topModule} write_verilog synth_output.v stat `; break; case "xilinx": synthScript = ` read_verilog design.v hierarchy -check -top ${topModule} synth_xilinx -top ${topModule} write_verilog synth_output.v stat `; break; default: synthScript = ` read_verilog design.v hierarchy -check -top ${topModule} synth -top ${topModule} techmap opt write_verilog synth_output.v stat `; } const scriptFile = join(projectDir, "synth.ys"); await fs.writeFile(scriptFile, synthScript); // Run Yosys const { stdout, stderr } = await execAsync(`yosys -s ${scriptFile}`, { cwd: projectDir, timeout: 120000, }); let synthVerilog = ""; try { synthVerilog = await fs.readFile(join(projectDir, "synth_output.v"), 'utf8'); } catch { synthVerilog = "Synthesis output not generated"; } return JSON.stringify({ project_id: projectId, success: true, stdout, stderr, synthesized_verilog: synthVerilog, target, }, null, 2); } catch (error: any) { return JSON.stringify({ success: false, error: error.message || String(error), }, null, 2); } }
- src/index.ts:729-747 (schema)The JSON schema defining the input parameters for the synthesize_verilog tool: verilog_code (required string), top_module (required string), target (optional string, default 'generic').inputSchema: { type: "object", properties: { verilog_code: { type: "string", description: "The Verilog source code to synthesize" }, top_module: { type: "string", description: "Name of the top-level module" }, target: { type: "string", description: "Target technology (generic, ice40, xilinx, intel)", default: "generic" }, }, required: ["verilog_code", "top_module"], },
- src/index.ts:726-748 (registration)Registration of the synthesize_verilog tool in the listTools response, including name, description, and inputSchema.{ name: "synthesize_verilog", description: "Synthesize Verilog code using Yosys for various FPGA targets", inputSchema: { type: "object", properties: { verilog_code: { type: "string", description: "The Verilog source code to synthesize" }, top_module: { type: "string", description: "Name of the top-level module" }, target: { type: "string", description: "Target technology (generic, ice40, xilinx, intel)", default: "generic" }, }, required: ["verilog_code", "top_module"], }, },
- src/index.ts:868-879 (registration)Dispatch handler in the CallToolRequestSchema that validates input parameters using helper functions and invokes the edaServer.synthesizeVerilog method.case "synthesize_verilog": { const verilogCode = validateRequiredString(args, "verilog_code", name); const topModule = validateRequiredString(args, "top_module", name); const target = getStringProperty(args, "target", "generic"); return { content: [{ type: "text", text: await edaServer.synthesizeVerilog(verilogCode, topModule, target), }], }; }