synthesize_verilog
Convert Verilog code into FPGA-compatible netlists using Yosys. Specify target technology (generic, ice40, xilinx, intel) and top module for precise synthesis.
Instructions
Synthesize Verilog code using Yosys for various FPGA targets
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| target | No | Target technology (generic, ice40, xilinx, intel) | generic |
| top_module | Yes | Name of the top-level module | |
| verilog_code | Yes | The Verilog source code to synthesize |