run_openlane
Execute the complete ASIC design flow from RTL to GDSII using OpenLane. Input Verilog code, design name, and clock specifications to generate results in under 10 minutes. Optionally open results in KLayout for analysis.
Instructions
Run complete ASIC design flow using OpenLane (RTL to GDSII). This process can take up to 10 minutes.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| clock_period | No | Clock period in nanoseconds | |
| clock_port | No | Name of the clock port | clk |
| design_name | Yes | Name of the design (will be used for module and files) | |
| open_in_klayout | No | Automatically open result in KLayout | |
| verilog_code | Yes | The Verilog RTL code for ASIC implementation |