run_openlane
Transform Verilog RTL code into GDSII for ASIC designs using OpenLane. Specify design parameters, clock details, and automate KLayout visualization. Complete flow in 10 minutes.
Instructions
Run complete ASIC design flow using OpenLane (RTL to GDSII). This process can take up to 10 minutes.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| clock_period | No | Clock period in nanoseconds | |
| clock_port | No | Name of the clock port | clk |
| design_name | Yes | Name of the design (will be used for module and files) | |
| open_in_klayout | No | Automatically open result in KLayout | |
| verilog_code | Yes | The Verilog RTL code for ASIC implementation |