verilog_simulate
Compile and run Verilog testbench simulations with iverilog and vvp, catching runtime assertions and testbench errors while preventing infinite loops via timeout.
Instructions
Compiles and runs a behavioral testbench simulation using iverilog + vvp. Captures runtime assertions ($fatal), testbench errors, and protects against infinite loops with a timeout.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| cwd | No | Optional working directory. | |
| files | Yes | List of Verilog source files including the design and testbench. | |
| dump_waves | No | Whether to record VCD waveforms. | |
| timeout_ms | No | Maximum simulation runtime in milliseconds before aborting (default: 15000). | |
| top_module | No | Name of the top-level testbench module. |