mcp-verilog
Server Configuration
Describes the environment variables required to run the server.
| Name | Required | Description | Default |
|---|---|---|---|
| MCP_VERILOG_RUNTIME | No | Set to 'host' to force host binaries instead of container execution. | podman |
Instructions
Guidance the server publishes about itself, which clients place ahead of the tool catalog so the model reads it before choosing anything.
This server publishes no instructions, or was last inspected before Glama recorded them.
Capabilities
Features and capabilities supported by this server
Protocol revision2025-11-25
| Capability | Details |
|---|---|
| tools | {} |
Tools
Functions exposed to the LLM to take actions
| Name | Description |
|---|---|
| verilog_lintA | Lints Verilog / SystemVerilog source files using verible-verilog-lint and returns structured line, column, severity, and rule diagnostics. |
| verilog_compileA | Performs syntax validation and elaboration checking on Verilog files using iverilog or verilator without running full simulation. |
| verilog_simulateA | Compiles and runs a behavioral testbench simulation using iverilog + vvp. Captures runtime assertions ($fatal), testbench errors, and protects against infinite loops with a timeout. |
| verilog_toolchain_infoA | Returns active container or host execution runtime info and versions of iverilog, verilator, verible, and sv2v. |
Prompts
Interactive templates invoked by user choice
| Name | Description |
|---|---|
No prompts | |
Resources
Contextual data attached and managed by the client
| Name | Description |
|---|---|
No resources | |
TDQS
Scored across 4 tools
Each tool targets a distinct stage of Verilog development: lint rules, compile/elaboration, simulation execution, and environment/version introspection. There is no meaningful overlap between these purposes.
All tools share the verilog_ prefix and use lowercase snake_case, making them easy to group. The first three are clearly verb-style actions, while verilog_toolchain_info is noun-style, a minor deviation from a strict verb_noun pattern.
Four tools is a well-scoped size for a Verilog toolchain server. Each tool covers a significant, non-redundant capability without bloating the API.
Lint, compile, simulate, and toolchain info cover the core hardware verification workflow well. A formatter such as verible-verilog-format or waveform/coverage retrieval would round out the surface, but agents can work around those gaps.