A
licenseNot graded
qualityB
maintenanceEnables AI agents to parse and query VCD/FSDB simulation waveforms, search signals, analyze AXI transactions, render ASCII timing diagrams, and check protocol compliance through structured MCP tools.
MIT
mcp-verilog
by zesun33
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TDQS
A4.1/5.0
Scored across 4 tools
Disambiguation5/5
Each tool targets a distinct stage of Verilog development: lint rules, compile/elaboration, simulation execution, and environment/version introspection. There is no meaningful overlap between these purposes.
Naming Consistency4/5
All tools share the verilog_ prefix and use lowercase snake_case, making them easy to group. The first three are clearly verb-style actions, while verilog_toolchain_info is noun-style, a minor deviation from a strict verb_noun pattern.
Tool Count5/5
Four tools is a well-scoped size for a Verilog toolchain server. Each tool covers a significant, non-redundant capability without bloating the API.
Completeness4/5
Lint, compile, simulate, and toolchain info cover the core hardware verification workflow well. A formatter such as verible-verilog-format or waveform/coverage retrieval would round out the surface, but agents can work around those gaps.
Maintenance
ActivityMaintained
ResponsivenessNo issues