verilog_compile

Does the description disclose side effects, auth requirements, rate limits, or destructive behavior?

No annotations are provided, so the description carries the full burden. It usefully discloses that full simulation is not run and names the compiler engines. However, it does not describe possible side effects, error behavior, or whether intermediate files are generated, which would matter without annotations.

Agents need to know what a tool does to the world before calling it. Descriptions should go beyond structured annotations to explain consequences.

Is the description appropriately sized, front-loaded, and free of redundancy?

The description is a single sentence with no filler. It front-loads the core purpose and includes the key exclusion ('without running full simulation') compactly.

Shorter descriptions cost fewer tokens and are easier for agents to parse. Every sentence should earn its place.

Given the tool's complexity, does the description cover enough for an agent to succeed on first attempt?

The schema is rich enough to cover all parameters, and the description states the tool's scope and non-simulation behavior. There is no output schema, and the description does not describe return values, but compiler success/error output is reasonably inferable for this kind of tool.

Complex tools with many parameters or behaviors need more documentation. Simple tools need less. This dimension scales expectations accordingly.

Does the description clarify parameter syntax, constraints, interactions, or defaults beyond what the schema provides?

The input schema covers 100% of the parameters, so the description does not need to repeat parameter details. It adds marginal value by mentioning iverilog and verilator, which aligns with the compiler parameter, but does not go beyond what the schema already documents.

Input schemas describe structure but not intent. Descriptions should explain non-obvious parameter relationships and valid value ranges.

Does the description clearly state what the tool does and how it differs from similar tools?

The description states a specific action ('syntax validation and elaboration checking') on a specific resource ('Verilog files') and explicitly distinguishes itself from full simulation, which separates it from the verilog_simulate sibling. It is clear and actionable.

Agents choose between tools based on descriptions. A clear purpose with a specific verb and resource helps agents select the right tool.

Does the description explain when to use this tool, when not to, or what alternatives exist?

The description gives clear context: use this for syntax/elaboration checking rather than full simulation. However, it does not explicitly mention when to prefer verilog_lint or verilog_simulate, nor does it state exclusions or alternatives by name.

Agents often have multiple tools that could apply. Explicit usage guidance like "use X instead of Y when Z" prevents misuse.