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synthesize_acceptance

Derive a machine-checked AcceptanceSpec from a synthesized FrameworkPlan and load it as the session's acceptance judge, generating no-fault, clock, NVIC, and GPIO checks.

Instructions

Auto-derive a machine-checked AcceptanceSpec from the synthesized FrameworkPlan (Pillar D Tier 3) and load it as the session's acceptance judge — welding design synthesis to the acceptance loop. Always emits a no_fault check (init must not HardFault); adds a memory_u32 bits_set check per clock the plan enables (RCC enable bit), a memory_u32 bits_set check per interrupt the plan enables (arch-standard NVIC ISER bit, from the resolved IRQ number), and a masked memory_u32 eq check per configured pin (GPIO MODER = AF/analog; F1's CRL/CRH is skipped). Register/IRQ/port placements come from the session's loaded SVD or explicit register_map/irq_map/gpio_map; anything unresolvable is surfaced, never guessed. Each derived check also carries source provenance (the init function + line that should satisfy it), so a later failure points straight at the fix site. Run design_framework first; load an SVD (start_debug_session/set svd) for clock/NVIC/GPIO checks.

Input Schema

TableJSON Schema
NameRequiredDescriptionDefault
loadNoLoad the derived spec as the session acceptance judge (default true).
nameNoOptional spec name.
irq_mapNoOptional explicit IRQ numbers {line_or_family: {irq_name: number}} (name with or without _IRQn); overrides the SVD.
sessionNoTarget session id (default 'default').
gpio_mapNoOptional explicit GPIO port bases {line_or_family: {port_letter: MODER_address}}; overrides the SVD.
stopped_atNoOptional symbol to also assert the PC reached after init (e.g. 'main').
include_gpioNoEmit GPIO MODER checks for configured pins (default true).
include_nvicNoEmit NVIC ISER checks for enabled interrupts (default true).
register_mapNoOptional explicit RCC placements {line_or_family: {clock: {address, bit}}}; overrides the SVD.
include_no_faultNoEmit the no_fault check (default true).

Schema Changelog

Changes observed during successful MCP inspections.

  1. First observedv0.15.1

TDQS

A4.3/5.0
Behavior5/5

Does the description disclose side effects, auth requirements, rate limits, or destructive behavior?

With annotations only covering the safety profile (readOnlyHint=false, destructiveHint=false, idempotentHint=false), the description adds substantial behavioral detail: exactly which checks are emitted (no_fault, per-clock RCC bits_set, per-IRQ NVIC ISER, per-pin GPIO MODER), that unresolvable items are surfaced rather than guessed, and that each check carries source provenance pointing at the fix site. This is rich context beyond the annotations.

Agents need to know what a tool does to the world before calling it. Descriptions should go beyond structured annotations to explain consequences.

Conciseness4/5

Is the description appropriately sized, front-loaded, and free of redundancy?

Front-loaded with the core purpose in the first sentence, followed by the emitted checks, provenance behavior, and prerequisites. It is dense and jargon-heavy with long parentheticals, but every sentence carries distinct information an agent needs.

Shorter descriptions cost fewer tokens and are easier for agents to parse. Every sentence should earn its place.

Completeness4/5

Given the tool's complexity, does the description cover enough for an agent to succeed on first attempt?

For a complex 10-parameter tool with no output schema, the description adequately explains what is produced (the derived check set and its provenance) and what setup is required. It does not detail the returned object's shape or failure semantics when nothing is resolvable, leaving a small gap.

Complex tools with many parameters or behaviors need more documentation. Simple tools need less. This dimension scales expectations accordingly.

Parameters3/5

Does the description clarify parameter syntax, constraints, interactions, or defaults beyond what the schema provides?

Schema coverage is 100%, so the schema already documents all 10 parameters, giving a baseline of 3. The description adds the SVD-vs-explicit-map precedence relationship (register_map/irq_map/gpio_map override the SVD), which is useful but largely mirrors what the schema descriptions already state.

Input schemas describe structure but not intent. Descriptions should explain non-obvious parameter relationships and valid value ranges.

Purpose5/5

Does the description clearly state what the tool does and how it differs from similar tools?

States a precise verb and resource: auto-derive a machine-checked AcceptanceSpec from the synthesized FrameworkPlan and load it as the session acceptance judge. It even distinguishes itself from siblings by referencing design_framework (the input producer) and the acceptance loop, so an agent knows this is the synthesis bridge, not load_acceptance or run_acceptance.

Agents choose between tools based on descriptions. A clear purpose with a specific verb and resource helps agents select the right tool.

Usage Guidelines4/5

Does the description explain when to use this tool, when not to, or what alternatives exist?

Gives explicit prerequisites: 'Run design_framework first; load an SVD (start_debug_session/set svd) for clock/NVIC/GPIO checks.' This names the ordering dependency and the setup alternative. It lacks an explicit when-not (e.g., 'if you already have a spec, use load_acceptance instead'), which keeps it from a 5.

Agents often have multiple tools that could apply. Explicit usage guidance like "use X instead of Y when Z" prevents misuse.