run_pipeline
Chains verified design tools in dependency order to turn a netlist and product spec into a flashable HAL skeleton and machine-checked acceptance spec, collecting unresolved gaps for build/verify.
Instructions
Spec-to-silicon capstone (Pillar G): run the whole deterministic DESIGN half in one call. Chains the existing, individually verified tools in dependency order -- import_netlist? -> import_spec? -> design_framework -> solve_clock_tree? -> solve_timer? -> render_framework -> synthesize_acceptance -- turning a netlist plus a product spec into a flashable HAL skeleton and a machine-checked acceptance spec, then hands off to the build/verify loop. Optional stages (marked ?) run only when their input is present. Honest by construction: it GUESSES NOTHING -- it sequences verified tools and aggregates every stage's own unresolved/conflict gaps into one 'human decisions / data still needed' list. A required-stage hard error (no board, invalid input) stops with pipeline_status=blocked at that stage; expected gaps (an AF needing a pin DB, an unmodelled clock) surface as complete_with_unresolved; a clean run is complete. Operates on the session's board unless netlist= is supplied.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| spec | No | Product spec object to import and design from (import_spec). | |
| style | No | Render style for the framework skeleton (default hal). | |
| af_map | No | Alternate-function map for GPIO AF resolution {line_or_family: {port_pin: {'PERIPH_SIG': af}}}. | |
| design | No | Peripheral config overrides merged into the design {PERIPH: {..}}. | |
| source | No | Clock source for solve_clock_tree (e.g. hse/hsi). | |
| db_path | No | Path to a pin-capability DB for AF resolution (else STM32_GDB_MCP_PIN_DB). | |
| irq_map | No | IRQ-number map for NVIC acceptance checks {line_or_family: {irq_name: number}}. | |
| netlist | No | Netlist to import first: {path|text, format?}. Omit to use the board already in this session. | |
| session | No | Optional debug-session name. Omit for the default target. | |
| gpio_map | No | GPIO base-address map for pin acceptance checks {line_or_family: {port_letter: base_address}}. | |
| source_hz | No | Clock source frequency in Hz for solve_clock_tree. | |
| sysclk_hz | No | Target SYSCLK in Hz; presence enables the solve_clock_tree stage. | |
| need_48mhz | No | Require a 48 MHz domain (USB/SDMMC) in the clock solve. | |
| stopped_at | No | Symbol the acceptance spec should assert the core halts at. | |
| synthesize | No | Set false to stop after render_framework and skip acceptance synthesis (default true). | |
| register_map | No | Clock-enable register map for acceptance placement {line_or_family: {clock: {address, bit}}}. | |
| acceptance_name | No | Name for the derived acceptance spec. |