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solve_clock_tree

Compute exact PLL dividers, bus prescalers, and flash wait-states from a clock source and target SYSCLK, then store the result so framework rendering emits real SystemClock_Config code.

Instructions

Synthesize a concrete SystemClock_Config() for the session's FrameworkPlan (Pillar D Tier 3) - the last hand-written gap in generated init code. Given a clock source (HSE + crystal Hz, or HSI) and a target SYSCLK, it computes the exact PLL dividers (M/N/P or R, Q for 48 MHz USB), AHB/APB bus prescalers, and flash wait-states via pure datasheet math, then stores the result so the next render_framework emits real clock code instead of a TODO stub. Deterministic and honest: an unmodelled device or an infeasible target is surfaced, never guessed. Built-in profiles: STM32F401/F407/F411 and mainstream L4 (<=80 MHz); pass an explicit profile for others. Run design_framework first.

Input Schema

TableJSON Schema
NameRequiredDescriptionDefault
loadNoStore the solution into the plan so render_framework uses it (default true).
sourceNoClock source: 'HSE' or 'HSI' (default 'HSI').
profileNoOptional explicit device profile; overrides the built-in table.
sessionNoTarget session id (default 'default').
source_hzNoHSE crystal frequency in Hz (required when source=HSE).
sysclk_hzNoTarget SYSCLK in Hz (e.g. 168000000).
need_48mhzNoRequire an exact 48 MHz PLL output for USB/SDIO/RNG (default false).

Schema Changelog

Changes observed during successful MCP inspections.

  1. First observedv0.15.1

TDQS

A4.3/5.0
Behavior4/5

Does the description disclose side effects, auth requirements, rate limits, or destructive behavior?

Annotations mark this as a non-read-only, non-idempotent write, and the description adds real context beyond them: the result is stored into the plan unless load=false, the math is 'pure datasheet math', and infeasible or unmodelled targets are surfaced rather than guessed. It never contradicts the annotations. The only gap is that the shape of a 'surfaced' failure is not described, which matters since there is no output schema.

Agents need to know what a tool does to the world before calling it. Descriptions should go beyond structured annotations to explain consequences.

Conciseness4/5

Is the description appropriately sized, front-loaded, and free of redundancy?

A single front-loaded paragraph that starts with the verb and the produced artifact, with zero bare filler. It is dense and carries some flavor phrasing ('the last hand-written gap in generated init code', 'Pillar D Tier 3') that slightly inflates length without adding invocation guidance.

Shorter descriptions cost fewer tokens and are easier for agents to parse. Every sentence should earn its place.

Completeness4/5

Given the tool's complexity, does the description cover enough for an agent to succeed on first attempt?

For a 7-parameter tool with no output schema, the description covers workflow position, scope limits, determinism guarantees, and the side effect of storing into the plan. Return-value semantics are only implied ('is surfaced'), which is the main remaining hole given the absent output schema.

Complex tools with many parameters or behaviors need more documentation. Simple tools need less. This dimension scales expectations accordingly.

Parameters4/5

Does the description clarify parameter syntax, constraints, interactions, or defaults beyond what the schema provides?

Schema description coverage is already 100%, so the baseline is 3; the description goes further by tying parameters together, explaining that HSE requires a crystal Hz value, that a 48 MHz target drives the R/Q branch, and what 'profile' overrides (the built-in device table). It adds cross-parameter meaning rather than restating field docs.

Input schemas describe structure but not intent. Descriptions should explain non-obvious parameter relationships and valid value ranges.

Purpose5/5

Does the description clearly state what the tool does and how it differs from similar tools?

The description names a specific verb and artifact: 'Synthesize a concrete SystemClock_Config()' for the session's FrameworkPlan, and spells out exactly what gets computed (PLL M/N/P or R/Q, AHB/APB prescalers, flash wait-states). This clearly distinguishes it from siblings like design_framework and solve_timer without needing to open any schema.

Agents choose between tools based on descriptions. A clear purpose with a specific verb and resource helps agents select the right tool.

Usage Guidelines4/5

Does the description explain when to use this tool, when not to, or what alternatives exist?

It states the prerequisite ('Run design_framework first') and the follow-on consumer ('the next render_framework emits real clock code'), plus the scope boundary that built-ins cover F401/F407/F411 and mainstream L4 <=80 MHz with an explicit profile needed otherwise. There is no explicit statement of when NOT to use it, so it falls just short of the top band.

Agents often have multiple tools that could apply. Explicit usage guidance like "use X instead of Y when Z" prevents misuse.