solve_clock_tree
Compute exact PLL dividers, bus prescalers, and flash wait-states from a clock source and target SYSCLK, then store the result so framework rendering emits real SystemClock_Config code.
Instructions
Synthesize a concrete SystemClock_Config() for the session's FrameworkPlan (Pillar D Tier 3) - the last hand-written gap in generated init code. Given a clock source (HSE + crystal Hz, or HSI) and a target SYSCLK, it computes the exact PLL dividers (M/N/P or R, Q for 48 MHz USB), AHB/APB bus prescalers, and flash wait-states via pure datasheet math, then stores the result so the next render_framework emits real clock code instead of a TODO stub. Deterministic and honest: an unmodelled device or an infeasible target is surfaced, never guessed. Built-in profiles: STM32F401/F407/F411 and mainstream L4 (<=80 MHz); pass an explicit profile for others. Run design_framework first.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| load | No | Store the solution into the plan so render_framework uses it (default true). | |
| source | No | Clock source: 'HSE' or 'HSI' (default 'HSI'). | |
| profile | No | Optional explicit device profile; overrides the built-in table. | |
| session | No | Target session id (default 'default'). | |
| source_hz | No | HSE crystal frequency in Hz (required when source=HSE). | |
| sysclk_hz | No | Target SYSCLK in Hz (e.g. 168000000). | |
| need_48mhz | No | Require an exact 48 MHz PLL output for USB/SDIO/RNG (default false). |