solve_timer
Computes timer Prescaler and Period (PSC/ARR) register values for a target update frequency using the solved TIMxCLK, returning exact or closest achievable frequency with ppm error.
Instructions
Solve a timer's Prescaler/Period (PSC/ARR) for a target update frequency (Pillar D Tier 3). Turns intent ('TIM3 at 1 kHz') into concrete register values using the timer input clock (TIMxCLK) derived from the solved clock tree. Record a target via design_framework(design={'TIM3': {'update_hz': 1000}}) then run solve_clock_tree first, or pass timer_clock_hz directly for a what-if. Deterministic and honest: an exact target yields zero-error PSC/ARR, an inexact one yields the closest pair plus the achieved frequency and ppm error, and an unrepresentable target or an unknown timer bus is surfaced, never guessed. Injects the result into the plan so render_framework emits concrete values instead of a TODO.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| bus | No | Override the timer's APB bus: 'apb1' or 'apb2'. | |
| load | No | Persist the solved PSC/ARR into the plan (default true). | |
| timer | No | Timer to solve, e.g. 'TIM3'. Omit to solve every timer that has a recorded target. | |
| session | No | Target session id (default 'default'). | |
| arr_bits | No | ARR width override: 16 or 32 (for 32-bit timers TIM2/TIM5). | |
| target_hz | No | Target update frequency in Hz; overrides the recorded design target (requires timer). | |
| timer_clock_hz | No | Explicit TIMxCLK in Hz; bypasses the clock-solution + bus derivation (pure what-if). |