cad_simulate
Compile and run HDL testbenches with Icarus Verilog, Verilator, or GHDL to return build diagnostics, runtime logs, and a waveform artifact for debugging.
Instructions
Compile and run an HDL testbench, returning diagnostics and a waveform artifact.
Tool call template
Replace each placeholder with a value matching the input schema. Only required parameters are included; add optional parameters as needed.
{
"id": 1,
"jsonrpc": "2.0",
"method": "tools/call",
"params": {
"arguments": {
"request": "<request>"
},
"name": "cad_simulate"
}
}Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| request | Yes |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| ok | Yes | ||
| job | Yes | ||
| top | No | ||
| error | No | ||
| engine | Yes | ||
| summary | No | ||
| warnings | No | ||
| waveform | No | ||
| artifacts | No | ||
| exit_code | No | ||
| timed_out | No | ||
| diagnostics | No | ||
| stderr_tail | No | ||
| stdout_tail | No | ||
| finish_reason | No | ||
| simulated_time | No |