cad_check
Parses, lints, or elaborates Verilog, SystemVerilog, or VHDL sources and returns normalized diagnostics to catch syntax and semantic issues before simulation or synthesis.
Instructions
Parse, lint, or elaborate HDL sources and return normalized diagnostics.
Tool call template
Replace each placeholder with a value matching the input schema. Only required parameters are included; add optional parameters as needed.
{
"id": 1,
"jsonrpc": "2.0",
"method": "tools/call",
"params": {
"arguments": {
"request": "<request>"
},
"name": "cad_check"
}
}Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| request | Yes |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| ok | Yes | ||
| job | Yes | ||
| top | No | ||
| error | No | ||
| level | Yes | ||
| counts | No | ||
| engines | No | ||
| summary | No | ||
| warnings | No | ||
| artifacts | No | ||
| hierarchy | No | ||
| unresolved | No | ||
| diagnostics | No |