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oss-cad-mcp

oss-cad-mcp

by ChalkCalliope
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    TDQS

    B3.3/5.0

    Scored across 15 tools

    Disambiguation4/5

    Each tool targets a distinct stage of the HDL flow (check, simulate, synthesize, verify, FPGA build, waveform, netlist, timing), so an agent can usually pick the right one from the description. The main fuzziness is cad_fpga_build, which internally subsumes synthesis and timing work also exposed by cad_synthesize and cad_timing, and cad_tool_run, which is a raw escape hatch that overlaps with every high-level workflow.

    Naming Consistency5/5

    All 15 tools share a uniform cad_<domain> snake_case pattern with no mixing of camelCase or stray verbs. The noun-oriented style (cad_job, cad_artifact, cad_tool_search) is applied consistently, and the nested cad_tool_* group reads predictably.

    Tool Count5/5

    15 tools is squarely in the well-scoped range for an FPGA/HDL toolchain covering distinct pipeline stages plus shared job/artifact plumbing. Each tool maps to a real capability rather than a granular CRUD variant, so none feel redundant padding.

    Completeness4/5

    The surface covers the full practical lifecycle: environment check, project setup, lint/elaborate, simulation with waveforms, synthesis, formal, FPGA bitstream with timing, plus job/artifact management and a discovery/help/run escape hatch for unexposed tools. Minor gaps remain, such as no explicit workspace cleanup/artifact deletion and no ASIC place-and-route or report-export operation, but agents can work around these via cad_tool_run.

    Maintenance

    ActivityMaintained
    ResponsivenessNo recent community issues

    Resources