oss-cad-mcp
Server Configuration
Describes the environment variables required to run the server.
| Name | Required | Description | Default |
|---|---|---|---|
| OSS_CAD_SUITE_ROOT | Yes | Path to the extracted OSS CAD Suite installation, for example /home/you/Kits/oss-cad-suite. | |
| OSS_CAD_MCP_WORKSPACE | No | Workspace directory for the server. Defaults to the server's current directory when not set. |
Instructions
Guidance the server publishes about itself, which clients place ahead of the tool catalog so the model reads it before choosing anything.
You are connected to an OSS CAD Suite toolchain through oss-cad-mcp.
Prefer intent-level tools over raw commands:
cad_status: check suite/workspace readiness first when unsure.
cad_project: inspect or validate the project and discover tops/testbenches/constraints.
cad_check: parse, lint, or elaborate SystemVerilog/Verilog/VHDL.
cad_simulate: compile and run a testbench; returns diagnostics and a waveform artifact.
cad_synthesize: Yosys synthesis with structured cell statistics.
cad_verify: SBY formal proof/BMC/cover, or EQY/MCY with an existing config.
cad_fpga_build: software-only iCE40/ECP5 synth -> PnR -> pack flow.
cad_waveform / cad_netlist / cad_timing: inspect generated artifacts.
cad_job: poll long-running jobs; a timed-out call returns a running job handle.
cad_tool_search / cad_tool_help / cad_tool_run: progressive disclosure for the rest of the 155-binary catalog.
Use cad_tool_run only when no workflow fits. Raw execution is disabled by default; enable
allow_raw only for trusted projects, and do not guess CLI flags (use cad_tool_help).
Each tool accepts one nested request object matching its published schema; for example
cad_status is called with {"request": {"deep": false}}.
Read artifact paths instead of re-running expensive tools. Hardware programming is
intentionally disabled in v0.1. Verified platform: Ubuntu 26.04 on WSL2 x86_64;
macOS and native Linux are not verified for full support.
Capabilities
Features and capabilities supported by this server
Protocol revision2025-11-25
| Capability | Details |
|---|---|
| tools | {
"listChanged": false
} |
| prompts | {
"listChanged": false
} |
| resources | {
"subscribe": false,
"listChanged": false
} |
Tools
Functions exposed to the LLM to take actions
| Name | Description |
|---|---|
| cad_statusB | Check the OSS CAD Suite installation, workspace, and tool capabilities. |
| cad_projectC | Inspect, initialize, or validate an HDL project. |
| cad_checkB | Parse, lint, or elaborate HDL sources and return normalized diagnostics. |
| cad_simulateB | Compile and run an HDL testbench, returning diagnostics and a waveform artifact. |
| cad_synthesizeB | Synthesize HDL with Yosys and return cell statistics and a JSON netlist. |
| cad_verifyC | Run formal verification with SBY, or EQY/MCY with an existing config. |
| cad_fpga_buildC | Build an iCE40/ECP5 bitstream: synthesis, place-and-route, packing, timing. |
| cad_waveformC | Inspect, sample, summarize, export, or convert VCD/FST waveforms. |
| cad_netlistB | Inspect a Yosys JSON netlist: stats, modules, cells, nets, fanout, or diff. |
| cad_timingB | Parse nextpnr/icetime timing reports, or run icetime on an .asc file. |
| cad_jobC | List, poll, wait for, log, or cancel server jobs. |
| cad_artifactC | List or read job artifacts and text files inside the workspace. |
| cad_tool_searchB | Search the complete OSS CAD Suite catalog, including tools not exposed as workflows. |
| cad_tool_helpB | Show curated help, version, examples, and risk notes for a suite tool. |
| cad_tool_runB | Run an allowlisted suite binary with argv. Prefer high-level workflows. |
Prompts
Interactive templates invoked by user choice
| Name | Description |
|---|---|
| debug_simulation | Debug a failing simulation using diagnostics and waveform evidence. |
| fix_lint | Fix lint and elaboration diagnostics before synthesis. |
| formal_verify | Prove or bound-check assertions with SBY. |
| build_fpga | Build a software-only iCE40/ECP5 bitstream and inspect timing. |
Resources
Contextual data attached and managed by the client
| Name | Description |
|---|---|
| catalog_resource | Complete OSS CAD Suite catalog. |
| catalog_families | Tool counts by family. |
| boards_resource | Software-build board presets. |
TDQS
Scored across 15 tools
Each tool targets a distinct stage of the HDL flow (check, simulate, synthesize, verify, FPGA build, waveform, netlist, timing), so an agent can usually pick the right one from the description. The main fuzziness is cad_fpga_build, which internally subsumes synthesis and timing work also exposed by cad_synthesize and cad_timing, and cad_tool_run, which is a raw escape hatch that overlaps with every high-level workflow.
All 15 tools share a uniform cad_<domain> snake_case pattern with no mixing of camelCase or stray verbs. The noun-oriented style (cad_job, cad_artifact, cad_tool_search) is applied consistently, and the nested cad_tool_* group reads predictably.
15 tools is squarely in the well-scoped range for an FPGA/HDL toolchain covering distinct pipeline stages plus shared job/artifact plumbing. Each tool maps to a real capability rather than a granular CRUD variant, so none feel redundant padding.
The surface covers the full practical lifecycle: environment check, project setup, lint/elaborate, simulation with waveforms, synthesis, formal, FPGA bitstream with timing, plus job/artifact management and a discovery/help/run escape hatch for unexposed tools. Minor gaps remain, such as no explicit workspace cleanup/artifact deletion and no ASIC place-and-route or report-export operation, but agents can work around these via cad_tool_run.