cad_fpga_build
Builds iCE40/ECP5 FPGA bitstreams from HDL sources by running synthesis, place-and-route, packing, and timing checks.
Instructions
Build an iCE40/ECP5 bitstream: synthesis, place-and-route, packing, timing.
Tool call template
Replace each placeholder with a value matching the input schema. Only required parameters are included; add optional parameters as needed.
{
"id": 1,
"jsonrpc": "2.0",
"method": "tools/call",
"params": {
"arguments": {
"request": "<request>"
},
"name": "cad_fpga_build"
}
}Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| request | Yes |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| ok | Yes | ||
| job | Yes | ||
| top | No | ||
| error | No | ||
| speed | No | ||
| device | No | ||
| family | Yes | ||
| stages | No | ||
| timing | No | ||
| package | No | ||
| summary | No | ||
| artifacts | No | ||
| bitstream | No | ||
| timing_met | No | ||
| utilization | No |