repair_project_setup
Reconcile RTL, XDC, simulation files, and compile order to repair or dry-run Project Mode setup, resolving file type and top-level mismatches.
Instructions
Dry-run or repair Project Mode setup by reconciling RTL, XDC, sim files, tops, SystemVerilog file types, and compile order.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| top | No | ||
| defines | No | ||
| dry_run | No | ||
| rtl_files | No | ||
| sim_files | No | ||
| simulator | No | ||
| timeout_s | No | ||
| xdc_files | No | ||
| include_dirs | No | ||
| project_path | No | ||
| testbench_top | No | ||
| target_language | No |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| ok | Yes | ||
| data | Yes | ||
| tool | Yes | ||
| message | Yes | ||
| summary | Yes | ||
| error_code | Yes | ||
| next_steps | No | ||
| raw_excerpt | No | ||
| next_actions | No | ||
| handoff_ready | Yes | ||
| stop_required | Yes | ||
| policy_allowed | No | ||
| resume_context | No | ||
| schema_version | Yes | ||
| assessment_status | Yes | ||
| handoff_reviewable | No | ||
| hardware_validation | No |