get_constraints_summary
Summarize Vivado XDC constraint files, ports, clocks, and common constraint commands to help agents understand project constraints and verify boardless FPGA designs.
Instructions
Summarize XDC files, ports, clocks, and common constraint commands.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| fileset | No | ||
| timeout_s | No |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| ok | Yes | ||
| data | Yes | ||
| tool | Yes | ||
| message | Yes | ||
| summary | Yes | ||
| error_code | Yes | ||
| next_steps | No | ||
| raw_excerpt | No | ||
| next_actions | No | ||
| handoff_ready | Yes | ||
| stop_required | Yes | ||
| policy_allowed | No | ||
| resume_context | No | ||
| schema_version | Yes | ||
| assessment_status | Yes | ||
| handoff_reviewable | No | ||
| hardware_validation | No |