openroad_pnr
Automate end-to-end ASIC physical design: floorplanning, placement, routing, and timing analysis on a gate-level netlist, returning area, utilization, wirelength, and slack metrics.
Instructions
Performs end-to-end automated digital ASIC physical design (floorplanning, placement, routing, and static timing analysis) on a gate-level netlist using OpenROAD, returning area, utilization, wirelength, and timing slack metrics.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| cwd | No | Optional working directory where source files reside. | |
| sdc_file | No | Optional SDC timing constraints file path. | |
| output_def | No | Optional output routed DEF file path. | |
| timeout_ms | No | Timeout in milliseconds (default: 45000). | |
| top_module | Yes | Name of the top-level module to place and route. | |
| netlist_file | Yes | Gate-level Verilog netlist file path. | |
| clock_period_ns | No | Target clock period in ns if no SDC provided (default: 1.0). | |
| core_utilization | No | Target core cell placement density from 0.0 to 1.0 (default: 0.4). |