@zesun33/mcp-openroad
Related Servers
Alternatives to @zesun33/mcp-openroad
No user-submitted related servers found.
Related Servers
- AlicenseAqualityBmaintenanceEnables AI coding agents and IDEs to synthesize Verilog/SystemVerilog designs with Yosys, inspect cell hierarchies and gate counts, and detect synthesis hazards like inferred latches and combinational loops before physical design flows.414 npmApache 2.0
- AlicenseAqualityDmaintenanceEnables AI assistants to perform Electronic Design Automation (EDA) tasks including Verilog synthesis, simulation, ASIC design flows, and waveform analysis through a unified interface.6ISC
- AlicenseAqualityCmaintenanceEnables AI coding agents and IDEs to run a complete open-source FPGA flow, including synthesis, place-and-route, bitstream generation, and safe hardware programming for iCE40/ECP5 boards.611 npmApache 2.0
- FlicenseNot gradedqualityCmaintenanceEnables multi-agent orchestration of digital IC design flows (DFT, synthesis, APR, STA, PV, IREM, thermal, SIPI) through natural language by integrating heterogeneous EDA tools into a unified, secure, and observable API space with per-agent knowledge bases and decision traceability.-
- AlicenseAqualityBmaintenanceEnables AI coding agents and IDEs to lint, compile, syntax-check, and simulate Verilog/SystemVerilog designs through structured, token-efficient MCP tools with isolated containerized toolchains.415 npmApache 2.0
- FlicenseNot gradedqualityAmaintenanceEnables AI coding agents such as Claude Code, Cursor, and Codex to drive a locally installed Xilinx Vivado through 32 curated tools covering sessions, synthesis, implementation, timing and CDC reports, XDC, IP, waveforms, and device programming. It also provides structured timing evidence with baseline comparison, offline VCD queries, environment self-diagnostics, and evidence-driven workflow prompts.-
TDQS
Scored across 6 tools
Each tool targets a distinct, non-overlapping stage of the ASIC physical design flow: floorplan, place, route, static timing analysis, or the full end-to-end PNR run. The info tool is clearly separated as a utility for runtime details. No ambiguity in purpose.
All tools follow a consistent 'openroad_' prefix with a lowercase action or stage identifier (pnr, floorplan, place, route, sta, toolchain_info). This creates a predictable and readable pattern that makes tool selection straightforward.
Six tools is well-scoped for a physical-design-oriented MCP server covering the main flow stages plus an end-to-end wrapper and an info utility. Each tool earns its place, supporting both granular control and a one-shot option.
The set covers the primary stages (floorplan, place, route, STA) and an end-to-end PNR path, which likely includes clock tree synthesis internally. A minor gap is the lack of a dedicated clock tree synthesis tool for users who need to run CTS in isolation, but the core lifecycle is otherwise complete.