Performs end-to-end automated digital ASIC physical design (floorplanning, placement, routing, and static timing analysis) on a gate-level netlist using OpenROAD, returning area, utilization, wirelength, and timing slack metrics.

Initializes ASIC floorplan boundaries, core/die sizing, and I/O pin placement using OpenROAD, generating a floorplan DEF file.

Performs standard cell global analytical placement (RePLace) and legalized detailed placement (DPL) on a floorplan DEF file.

Performs global routing (FastRoute) and detailed routing on a placed DEF file, reporting wirelength and DRC violation metrics.

Performs static timing analysis using OpenSTA on placed or routed DEF files, reporting Worst Negative Slack (WNS), Total Negative Slack (TNS), and critical paths.

Returns active container/host runtime and version information for OpenROAD, OpenSTA, and supported platform PDKs.