openroad_floorplan
Initialize ASIC floorplan boundaries, core/die sizing, and I/O pin placement, producing a floorplan DEF file to kickstart physical design.
Instructions
Initializes ASIC floorplan boundaries, core/die sizing, and I/O pin placement using OpenROAD, generating a floorplan DEF file.
Tool call template
Replace each placeholder with a value matching the input schema. Only required parameters are included; add optional parameters as needed.
{
"id": 1,
"jsonrpc": "2.0",
"method": "tools/call",
"params": {
"arguments": {
"netlist_file": "<netlist_file>",
"top_module": "<top_module>"
},
"name": "openroad_floorplan"
}
}Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| cwd | No | Optional working directory. | |
| die_width | No | Die width in microns (default: 60). | |
| die_height | No | Die height in microns (default: 60). | |
| output_def | No | Output floorplan DEF file path. | |
| timeout_ms | No | Timeout in milliseconds. | |
| top_module | Yes | Name of the top-level module. | |
| core_margin | No | Margin between die and core in microns (default: 5). | |
| netlist_file | Yes | Gate-level Verilog netlist file path. |