logisim_build
Draw a new Logisim circuit from a netlist and save it as .circ. It automatically places and wires components, verifies connections, and renders an image.
Instructions
Draw a NEW Logisim circuit from a netlist and save it as .circ (an existing file is only replaced with overwrite: true; to change an existing hand-drawn circuit, describe it with logisim_inspect first). Placement (signal flows left to right) and wiring are automatic; the file is then loaded back into Logisim to confirm every connection, checked for mistakes and rendered as an image.
components: [{"id": "A", "type": "input"}, {"id": "g1", "type": "and", "inputs": 3}, ...] id: Latin identifier, unique; it is also the label of pins, LEDs, probes and clocks. type: input, output, clock, constant, led, probe, button, dipswitch, not, buffer, and, or, nand, nor, xor, xnor, mux, demux, decoder, encoder, adder, subtractor, multiplier, comparator, shifter, negator, dff, tff, jkff, srff, register, counter, shiftregister, ram, rom, splitter, tunnel, hexdisplay, sevensegment (or any exact Logisim name; see logisim_components for ports and attributes). optional: width (bits), inputs (gate inputs), value (constant), select (mux/decoder select bits), fanout (splitter), facing, label, caption (free text shown next to it, any language), column (0 = leftmost column), at [x, y] (manual position, px), attrs {raw Logisim attributes}. connections: ["A -> g1.in0, g2.a", "g1 -> F", "clk: CLK -> ff1.clk, ff2.clk", "X, Y.in"] "source -> sink, sink"; a port is id.port. A bare id means the component's only port (pins, LEDs, clocks, constants) or its only output (left of ->) / only input (right of ->). Connections that share a port merge. Port names: gates out, in0..in(n-1) (also a, b, c...); not/buffer out, in; mux in0.., sel, out (en); decoder out0.., sel; adder/subtractor a, b, out, cin/bin, cout/bout; comparator a, b, gt, eq, lt; dff d, clk, q, nq, clr, pre; tff t, ...; jkff j, k, clk, q, nq, clr, pre; srff s, r, clk, q, nq, clr, pre; register q, d, clk, clr, en; counter q, d, clk, clr, load, ud, en, carry; splitter bus, b0..b(n-1); ram addr, out, in, ld, st, clk; rom addr, out; dipswitch s1..sN; any port also as #index. tunnels: nets drawn with labelled tunnels instead of long wires, by net name or source id (e.g. ["CLK"]). rails: input pin ids (and ids of NOT gates fed directly by such a pin) drawn textbook style: the pins stand at the top left and each signal runs down the page as a vertical bus that gates tap with horizontal branches. Recommended for combinational logic, e.g. ["A", "nA", "B", "nB", "C"]. title: text above the circuit.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| path | Yes | Path to the .circ file (absolute, or relative to the working folder) | |
| check | No | Simulate to find conflicts/oscillation (default true) | |
| rails | No | ||
| scale | No | Image scale (default 1.5, reduced automatically for large circuits) | |
| title | No | ||
| render | No | Return a picture (default true) | |
| tunnels | No | ||
| overwrite | No | Replace the file if it already exists (default false) | |
| components | Yes | ||
| connections | Yes |