Draw a NEW Logisim circuit from a netlist and save it as .circ (an existing file is only replaced with overwrite: true; to change an existing hand-drawn circuit, describe it with logisim_inspect first). Placement (signal flows left to right) and wiring are automatic; the file is then loaded back into Logisim to confirm every connection, checked for mistakes and rendered as an image.

components: [{"id": "A", "type": "input"}, {"id": "g1", "type": "and", "inputs": 3}, ...] id: Latin identifier, unique; it is also the label of pins, LEDs, probes and clocks. type: input, output, clock, constant, led, probe, button, dipswitch, not, buffer, and, or, nand, nor, xor, xnor, mux, demux, decoder, encoder, adder, subtractor, multiplier, comparator, shifter, negator, dff, tff, jkff, srff, register, counter, shiftregister, ram, rom, splitter, tunnel, hexdisplay, sevensegment (or any exact Logisim name; see logisim_components for ports and attributes). optional: width (bits), inputs (gate inputs), value (constant), select (mux/decoder select bits), fanout (splitter), facing, label, caption (free text shown next to it, any language), column (0 = leftmost column), at [x, y] (manual position, px), attrs {raw Logisim attributes}. connections: ["A -> g1.in0, g2.a", "g1 -> F", "clk: CLK -> ff1.clk, ff2.clk", "X, Y.in"] "source -> sink, sink"; a port is id.port. A bare id means the component's only port (pins, LEDs, clocks, constants) or its only output (left of ->) / only input (right of ->). Connections that share a port merge. Port names: gates out, in0..in(n-1) (also a, b, c...); not/buffer out, in; mux in0.., sel, out (en); decoder out0.., sel; adder/subtractor a, b, out, cin/bin, cout/bout; comparator a, b, gt, eq, lt; dff d, clk, q, nq, clr, pre; tff t, ...; jkff j, k, clk, q, nq, clr, pre; srff s, r, clk, q, nq, clr, pre; register q, d, clk, clr, en; counter q, d, clk, clr, load, ud, en, carry; splitter bus, b0..b(n-1); ram addr, out, in, ld, st, clk; rom addr, out; dipswitch s1..sN; any port also as #index. tunnels: nets drawn with labelled tunnels instead of long wires, by net name or source id (e.g. ["CLK"]). rails: input pin ids (and ids of NOT gates fed directly by such a pin) drawn textbook style: the pins stand at the top left and each signal runs down the page as a vertical bus that gates tap with horizontal branches. Recommended for combinational logic, e.g. ["A", "nA", "B", "nB", "C"]. title: text above the circuit.

Synthesize a combinational circuit from Boolean formulas or a truth table, in a chosen gate basis, then draw it (like logisim_build) and verify it by simulating every input combination.

outputs: {"F": "A & ~B | C", "G": "A ^ B ^ C"}; formula syntax: & * · ∧ AND, | + ∨ OR, ~ ! ¬ NOT or postfix ', ^ ⊕ XOR, ↑ NAND, ↓ NOR, -> → implication, <-> == ≡ equivalence, 0/1, parentheses. An output can instead be {"minterms": [1, 3, 7], "dont_care": [5]} (then 'inputs' is required; inputs[0] is the most significant bit). truth_table: alternative to outputs, text like "A B C | F G\n0 0 0 | 0 1\n..." (x or - = don't care, missing rows = don't care). form: as_written (formulas only; default for formulas), min_sop (minimal DNF; default for tables/minterms), min_pos (minimal CNF), sop_canonical (perfect DNF), pos_canonical (perfect CNF). basis: any (default), and_or_not, nand (NAND only), nor (NOR only). max_inputs: gate fan-in limit (default 4; 2 = two-input gates).

Find wiring mistakes in a circuit: unconnected inputs, floating nets, several outputs on one net (often an accidental short), wires passing straight through a port or drawn on top of each other (Logisim connects those), loose wire ends, bit width mismatches, lonely tunnels, overlapping parts; then simulate it (all input combinations when small) to find conflicts (E), undefined outputs (x) and oscillation.

List the component types logisim_build understands, with their port names; or, with 'type', show one type in detail: ports (name, direction, width, offset), attributes with defaults and allowed values.

Read a .circ file: list its circuits, components (with port names, as used by logisim_build) and the nets connecting them, as Logisim itself sees them.

Render a circuit as a PNG picture (wire colours show values), optionally after setting inputs or running steps; optionally save the picture to a file.

Run a circuit step by step: each step sets input pins, then runs 'clock' full clock cycles (all Clock components low->high->low). Returns a trace with one row per clock cycle (or per step without clock) of every output pin, LED and probe; values are decimal, or bit strings with x (undefined) and E (conflict). Optionally renders the final state.

Simulate every combination of the input pins (max 16 bits; multi-bit pins count all their bits) and return the truth table of all outputs, LEDs and probes, plus the minimal DNF/CNF formula of each 1-bit output.

Check that a circuit behaves as expected. Give exactly one of: expressions {output: formula} (checked on every input combination), truth_table (text 'A B | F' with rows '0 1 | 1', x = don't care), rows [{"A": 1, "B": 0, "F": 1}, ...], or sequence [{"set": {...}, "clock": 1, "expect": {...}}, ...] for clocked circuits (state carries over between steps). Names are pin/LED/probe labels.