load_vhdl
Load VHDL design files into the active session to elaborate a two-state RTL subset, then query hierarchy, connectivity, and source references across the design.
Instructions
Load VHDL into the active session (beta, restricted two-state RTL subset). Prefer passing every file of the design as one list (any order; units are resolved across files). Single-file calls still work: load package files first, then the top. Package-only files or entities awaiting generics may return top=null. Use hierarchy, cards and connectivity queries on the elaborated design. Use get_source for entity, port, signal, instance and process source references. intent=True enables get_intent for enum literals, record fields, generics and symbolic ranges. Unsupported constructs may fail during beta development. Returns the top summary when elaborated, language and beta status.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| top | No | Top entity name; omit to infer the top. | |
| file | Yes | A local VHDL source path (.vhd/.vhdl), or a list of paths loaded as one batch in any order. | |
| intent | No | Retain VHDL source intent for get_intent; the last load_vhdl call decides whether it stays live. | |
| library | No | VHDL library the files compile into, for designs that name it, as in `library neorv32;`. Omit for designs that use `work`. |