load_liberty
Registers standard-cell models from local Liberty .lib files in the active session, enabling gate netlist elaboration when those cells are instantiated.
Instructions
Register standard-cell models from local Liberty .lib files in the
active session. Use this before load_verilog when a gate netlist instantiates
those cells; use load_primitives instead for the built-in Xilinx or Yosys
model sets. This changes session state and returns {"ok": true}.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| files | Yes | One or more local Liberty .lib file paths. |