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naja-scope

naja-scope

by keplertech
OverviewSchemaSourceRelated ServersDiscussionsAdmin
Python
Hybrid

load_systemverilog

Elaborates local SystemVerilog RTL into the active design session so agents can query post-elaboration hierarchy, connectivity, and module structure.

Instructions

Elaborate local SystemVerilog sources into the active design session. Use this for SystemVerilog RTL; use load_vhdl for VHDL (beta), or load_verilog with load_liberty/load_primitives for a structural gate netlist. Requires at least files or flist and changes the in-memory design session. Anonymous lowered objects are addressable by #. defines are preprocessor -D entries ("NAME" or "NAME=VALUE"). allow_unknown_designs=True blackboxes any module still undefined instead of failing (e.g. undelivered hard macros in a partly-open-source design). blackbox_multi_writer_memories does the same for modules whose multi-writer memories naja cannot infer. intent=True retains naja's in-engine SNL↔slang link for get_intent.

Input Schema

NameRequiredDescriptionDefault
topNoTop module name; omit to use najaeda's inferred top.
filesNoLocal SystemVerilog source file paths; optional when flist is provided.
flistNoPath to a simulator-style file list; optional when files are provided.
intentNoRetain the live SNL-to-slang link required by get_intent; uses more memory.
definesNoPreprocessor definitions as "NAME" or "NAME=VALUE" entries.
keep_assignsNoPreserve continuous assignments as explicit lowered objects.
default_timescaleNoFallback time scale for modules without an explicit time unit, e.g. 1ns/1ps; omit to use the frontend default.
allow_unknown_designsNoBlack-box unresolved module definitions instead of failing elaboration.
blackbox_multi_writer_memoriesNoBlack-box whole modules whose memories have unsupported multiple writers instead of failing.

Schema Changelog

Changes observed during successful MCP inspections.

  1. Changed1 schema field changed
    • addedInput schema / properties / default_timescale
      Added value: +{
+  "anyOf": [
+    {
+      "type": "string"
+    },
+    {
+      "type": "null"
+    }
+  ],
+  "default": null,
+  "description": "Fallback time scale for modules without an explicit time unit, e.g. 1ns/1ps; omit to use the frontend default.",
+  "title": "Default Timescale"
+}
  2. Changed1 schema field changed
    • addedInput schema / properties / blackbox_multi_writer_memories
      Added value: +{
+  "default": false,
+  "description": "Black-box whole modules whose memories have unsupported multiple writers instead of failing.",
+  "title": "Blackbox Multi Writer Memories",
+  "type": "boolean"
+}
  3. Changed7 schema fields changedv0.1.9
    • addedInput schema / properties / allow_unknown_designs
      Added value: +{
+  "default": false,
+  "description": "Black-box unresolved module definitions instead of failing elaboration.",
+  "title": "Allow Unknown Designs",
+  "type": "boolean"
+}
    • addedInput schema / properties / defines
      Added value: +{
+  "anyOf": [
+    {
+      "items": {
+        "type": "string"
+      },
+      "type": "array"
+    },
+    {
+      "type": "null"
+    }
+  ],
+  "default": null,
+  "description": "Preprocessor definitions as \"NAME\" or \"NAME=VALUE\" entries.",
+  "title": "Defines"
+}
    • addedInput schema / properties / files / description
      Added value: +"Local SystemVerilog source file paths; optional when flist is provided."
    • addedInput schema / properties / flist / description
      Added value: +"Path to a simulator-style file list; optional when files are provided."
    • addedInput schema / properties / intent / description
      Added value: +"Retain the live SNL-to-slang link required by get_intent; uses more memory."
    • addedInput schema / properties / keep_assigns / description
      Added value: +"Preserve continuous assignments as explicit lowered objects."
    • addedInput schema / properties / top / description
      Added value: +"Top module name; omit to use najaeda's inferred top."
  4. First observedv0.1.8

TDQS

A4.8/5.0
Behavior5/5

Does the description disclose side effects, auth requirements, rate limits, or destructive behavior?

Annotations only give the generic write/idempotency profile; the description adds real behavioral context beyond them: the in-memory session is mutated, anonymous lowered objects are addressable by #<id>, allow_unknown_designs and blackbox_multi_writer_memories convert failures into blackboxes, and intent=True trades memory for the SNL↔slang link. That is materially more than the annotations convey.

Agents need to know what a tool does to the world before calling it. Descriptions should go beyond structured annotations to explain consequences.

Conciseness4/5

Is the description appropriately sized, front-loaded, and free of redundancy?

Front-loaded with the core action and the sibling routing before parameter detail, which is the right order. It is dense for eight sentences, but this is a nine-parameter elaboration tool and each clause carries operational meaning; only the intent/blackbox restatements are mildly redundant.

Shorter descriptions cost fewer tokens and are easier for agents to parse. Every sentence should earn its place.

Completeness5/5

Given the tool's complexity, does the description cover enough for an agent to succeed on first attempt?

With no output schema, the description still covers side effects (session mutation), failure-mode controls, addressing of results, and the memory tradeoff of intent=True. An agent has enough to call it correctly and anticipate the effect on the design session.

Complex tools with many parameters or behaviors need more documentation. Simple tools need less. This dimension scales expectations accordingly.

Parameters4/5

Does the description clarify parameter syntax, constraints, interactions, or defaults beyond what the schema provides?

Schema coverage is 100%, so the baseline is 3, and several description clauses (intent memory cost, blackbox flags) restate schema text. It still earns above baseline by giving the defines entry syntax and a concrete motivating scenario for blackboxing ('undelivered hard macros in a partly-open-source design').

Input schemas describe structure but not intent. Descriptions should explain non-obvious parameter relationships and valid value ranges.

Purpose5/5

Does the description clearly state what the tool does and how it differs from similar tools?

Opens with a specific verb and resource ('Elaborate local SystemVerilog sources') plus the target ('active design session'), and immediately contrasts itself with load_vhdl and load_verilog + load_liberty/load_primitives. An agent can pick it out from siblings without opening a schema.

Agents choose between tools based on descriptions. A clear purpose with a specific verb and resource helps agents select the right tool.

Usage Guidelines5/5

Does the description explain when to use this tool, when not to, or what alternatives exist?

Explicitly states when to use it (SystemVerilog RTL), when to use each alternative (load_vhdl for VHDL, load_verilog plus load_liberty/load_primitives for a structural gate netlist), and the entry precondition ('Requires at least files or flist'). Nothing is left to inference.

Agents often have multiple tools that could apply. Explicit usage guidance like "use X instead of Y when Z" prevents misuse.

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