load_verilog
Load local gate-level or structural Verilog into the active session. First call load_liberty for Liberty cells or load_primitives for built-ins; use load_systemverilog instead for RTL elaboration.
Instructions
Load local gate-level or structural Verilog into the active session.
First call load_liberty for Liberty cells or load_primitives for built-ins;
use load_systemverilog instead for RTL elaboration. Unknown modules fail
unless allow_unknown_designs is true. get_source shows the netlist
declaration of an object; for Yosys output, yosys_source_attributes=True
also records its RTL origins (get_source origin=N). get_intent cannot
answer for netlists.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| files | Yes | One or more local structural Verilog netlist paths. | |
| keep_assigns | No | Preserve continuous assignments as explicit objects. | |
| allow_unknown_designs | No | Black-box unresolved cell/module definitions instead of failing. | |
| yosys_source_attributes | No | Decode Yosys `(* src = ... *)` attributes into source origins pointing back to the RTL. |