set_cache_read
Enable or disable cache-aware memory reads to access cached data from the CPU viewpoint, essential for debugging code that modifies cached memory.
Instructions
Enable or disable cache-aware memory reads.
When ON, the default data access class (D:) shows cached data from the CPU's point of view instead of stale bus-level data. Essential for debugging code that modifies cached memory (e.g., LMU on TC39x).
Args: enabled: True to enable cache-aware reads, False to disable
Returns: Confirmation
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| enabled | No |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| result | Yes |