read_memory_cached
Read memory as the CPU sees it through its data cache, bypassing stale bus values. Essential for debugging cached memory modifications like shared variables.
Instructions
Read memory using cache-aware access (D: prefix).
Shows data as the CPU sees it through its data cache, not the stale value on the bus. Essential for debugging code that modifies cached memory (e.g., shared variables in LMU on TC39x).
Args: address: Memory address as hex string (e.g., "0x80000000") length: Number of bytes to read width: Access width in bits — 8, 16, 32, or 64 (default: 32)
Returns: Hex dump of cached memory contents
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| width | No | ||
| length | Yes | ||
| address | Yes |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| result | Yes |